Datasheet

Chapter 1: Introduction
1-9
1-2 Chipset Overview
The Intel 3000 chipset, designed for use with UP Pentium 4 and Dual Core Pentium
D Processors, is comprised of two primary components: the Memory Controller Hub
(MCH) and the I/O Controller Hub (ICH7R). With the capabilities provided by the
Intel 3000 chipset, the PDSML-LN1+/PDSML-LN2+ provides the performance and
feature-set required for cost-effective UP servers.
Memory Controller Hub (MCH)
The function of the MCH is to manage the data fl ow between four interfaces: the pro-
cessor interface (FSB), the System Memory Interface (DRAM Controller), the Direct
Media Interface (DMI) and the PCI Express Interface. The MCH is optimized for the
Pentium 4 or Pentium D processor in the LGA775 Land Grid Array Package.
Using a scalable FSB Vcc_CPU, the MCH supports FSB speed up to 1066 MT/s
(266 MHz). The Host Interface features supported include: Hyper-Threading Tech-
nology (HT), Pentium 4 and Pentium D processor FSB interrupt delivery, FSB
Dynamic Bus Inversion (DBI). It integrates a system memory DDR2 controller with
two 64-bit interfaces and supports one or two channels of DDR2 SDRAM.
The I/O Controller (ICH7R) provides the data buffering and interface arbitration re-
quired for the system to operate effi ciently. It also provides the bandwidth needed
for the system to maintain its peak performance. The Direct Media Interface (DMI)
provides the chip-to-chip connection between the MCH and the ICH7R.
The ICH7R supports up to four Serial ATA ports, six USB 2.0 ports and two IDE
devices. In addition, the ICH7R offers the Intel Matrix Storage Technology which
provides various RAID options for data protection and rapid data access. It also
supports the next generation of client management through the use of PROActive
technology in conjunction with Intel's next generation Gigabit Ethernet controller.
Intel ICH7 (ICH7R) System Features
The I/O Controller Hub provides the I/O subsystem with access to the rest of the
system. Functions and capabilities include:
*Advanced Confi guration and Power Interface, Version 2.0 (ACPI)
*Intel I/O External Design Specifi cation (EDS)
* The Intel 3000 Memory Controller Hub (MCH) External Design Specifi cation
(EDS)
*Intel I/O Controller Hub 7 (ICH7R) Thermal Design Guideline