Datasheet

Datasheet 31
2.11.2 Die Voltage Validation
Overshoot events from application testing on processor must meet the specifications in Table 11
when measured across the VCCSENSE and VSSSENSE pins. Overshoot events that are < 10 ns in
duration may be ignored. These measurement of processor die level overshoot should be taken with
a 100 MHz bandwidth limited oscilloscope.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These parameters are based on design characterization and are not tested.
3. Leakage to V
SS
with pin held at V
TT
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. The V
TT
represented in these specifications refers to instantaneous V
TT
.
3. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. V
IH
and V
OH
may experience excursions above V
TT
.
6. Refer to Ta b l e 6 to determine which signals include additional on-die termination resistance (R
L
).
7. Leakage to V
SS
with pin held at V
TT
.
8. Leakage to V
TT
with pin held at 300 mV.
Table 12. BSEL[1:0] and VID[5:0] Signal Group DC Specifications
Symbol Parameter Min. Typ. Max Units Notes
1
R
ON
BSEL[1:0] and VID[5:0]
Buffer On Resistance
N/A 60 W 2
I
OL
Maximum Pin Current N/A 8 mA 2
I
LO
Output Leakage Current N/A 200 µA 2,3
R
PULL_UP
Pull-Up Resistor 500 W
V
TOL
Voltage Tolerance 0.95 * V
TT
V
TT
1.05 * V
TT
V
Table 13. AGTL+ Signal Group DC Specifications
Symbol Parameter Min. Max. Unit Notes
1
V
IL
Input Low Voltage 0.0 GTLREF - (0.10 * V
TT
)V 2,3
V
IH
Input High Voltage GTLREF +
(0.10 * V
TT
)
V
TT
V 2,4,5
V
OH
Output High Voltage 0.90 * V
TT
V
TT
V2,5
I
OL
Output Low Current N/A V
TT
/
(0.50 * R
TT_MIN
+
[R
ON_MIN
|| R
L
])
mA 2,6
I
LI
Input Leakage Current N/A ± 200 µA 7,8
I
LO
Output Leakage Current N/A ± 200 µA 7,8
R
ON
Buffer On Resistance 7 11 W