Datasheet

Datasheet 29
NOTES:
1. The V
CC_MIN
and V
CC_MAX
loadlines represent static and transient limits. Please see Section 2.11.1 for V
CC
overshoot specifications.
2. The V
CC_MIN
and V
CC_MAX
loadlines are plots of the discrete point found in Ta bl e 10 .
3. Refer to Ta b le 9 for processor VID information.
4. The loadlines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor V
CC
and V
SS
pins. Refer to
the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.0 Design
Guidelines for socket loadline guidelines and VR implementation.
Figure 3. V
CC
Static and Transient Tolerance
VID - 0.000
VID - 0.020
VID - 0.040
VID - 0.060
VID - 0.080
VID - 0.100
VID - 0.120
VID - 0.140
VID - 0.160
VID - 0.180
VID - 0.200
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120
Icc [A]
Vcc [V]
V
CC
Typical
V
CC
Maximum
V
CC
Minimum