User`s manual

Chapter 2: Overview
2-11
2-2 Chipset Overview
Built upon the functionality and the capability of the Intel 7500 platform, the
X8QB6-F/X8QBE-F motherboard provides the performance and support for
quad_processor-based HPC/Cluster/Database servers. The 7500 platform con-
sists of the 7500 Series Socket-LS (LGA 1567) processor, the 7500 (IOH), and
the ICH10R (South Bridge).
With the Intel QuickPath interconnect (QPI) controller built in, the 7500 Series
processor offers point-to-point system interconnect interface, enhancing system
performance by utilizing serial link interconnections with increased bandwidth
and scalability.
The 7500 IO Hub provides the interface between QPI-based processor, and
industry-standard PCI-Express components. Each processor supports four full-
width, bidirectional interconnects that run at the speed of 4.8 GT/s, 5.86 GT/s or
6.4 GT/s. Each QPI link consists of 20 pairs of unidirectional differential lanes for
data transmission in addition to a differential forwarded clock. The two x16 PCI
Express Gen 2 connections can also be con gured as x8 and x4 links to comply
with PCI-E Base Speci cation, Rev. 2.0. These PCI-E Gen 2 lanes support peer-
to-peer read and write transactions. In addition, the legacy IOH provides a x4 ESI
(Enterprise South Bridge Interface) link support for the legacy bridge.
The 7500 chipset also offers a wide range of ESI, Intel® I/OAT Gen 3, Intel
VT-d and RAS (Reliability, Availability and Serviceability) support. The features
supported include memory interface ECC, x4/x8 Single Device Data Correction
(SDDC), Flow-through CRC (Cyclic Redundancy Check), parity protection, out-
of-band register access via SMBus, memory mirroring, and Hot-plug support on
the PCI-Express Interface.
Main Features of the 7500 Platform
Fully-connectivity (with four Intel® QuickPath Interconnects and up to eight cores
in each socket with 24MB of shared last level (L3) cache supported)
CPU-Integrated memory controller with support of DDR-3 1066 MHz RDIMMS
running at 800/978/1066 MHz via a memory buffer
Virtualization Technology, Integrated Manageability Engine (ME) supported
44 bits physical address and 48 bits virtual address supported