User`s manual

2-18
X8DTT-H+/-HF+/-HEF+/-HIBXF+/-HIBQF+ User's Manual
JBT1
FAN1
LEB1
LEB2
JLPC80
USB2/3
LE4
SW1
JWD
JBMC1
JPG1
JPL1
JPL2
JBAT1
JNMI1
JRST1
JSPK1
USB0/1
IPMI_LAN
CMOS
CLEAR
P1 DIMM1A
P1 DIMM1B
P1 DIMM2A
P1 DIMM2B
P1 DIMM3B
P1 DIMM3A
InfinBand
P2 DIMM2A
P2 DIMM2B
P2 DIMM1A
P2 DIMM1B
CPU1
CPU2
I-SATA1
LAN1
LAN2
IPMB
COM1
VGA
Battery
P2 DIMM3A
P2 DIMM3B
Slot 1 PCI-E 2.0 x16
Connector
Winbond
WPCM450
InfiniBand
CTRL
LAN CTRL1
LAN CTRL2
PHY
Intel 5520 (IOH-36D)
Intel ICH10R
South Bridge
BIOS
PWR Supply
FP CTRL
X8DTT-H+
LE1
LE3
JF2
LE2
Rev. 2.0
Intel 5500 (IOH-24D)
(For OEM only)
JPEN1
JTPM1
JUSB2
JPB
J119
JP5 JP7
SXB1:PCI-E 2.0 X8
J3
B
A
A. NMI Header
B. Internal Speaker
Internal Buzzer
The Internal Buzzer, located at JSPK1, can be
used to provide audible alarms for various beep
codes. See the table on the right for pin defi ni-
tions. Refer to the layout below for the locations
of the Internal Speaker/Buzzer.
Internal Buzzer
Pin Defi nitions
Pin# Defi nitions
Pin 1 Pos. (+) Beep In
Pin 2 Neg. (-) Alarm Speaker
NMI Header
The non-maskable interrupt header is located
at JNMI1. Refer to the table on the right for
pin defi nitions.
NMI Button
Pin Defi nitions (JF1)
Pin# Defi nition
1 Control
2 Ground
2-6 Connecting Cables
PWR SMB
Pin Defi nitions
Pin# Defi nition
1 Clock
2 Data
3 PWR Fail
4 Ground