User`s manual

Chapter 2: Installation
2-13
Universal Serial Bus
(USB0/1)
Two USB 2.0 ports (JPUSB1) are
located beside the PS/2 keyboard/
mouse ports. USB0 is the bottom
connector and USB1 is the top
connector. See the table on the
right for pin definitions.
Universal Serial Bus Pin Definitions
Pin
Number Definition
1+5V
2P0-
3P0+
4 Ground
5 N/A
Pin
Number Definitio
n
1+5V
2P0-
3P0+
4 Ground
5Key
USB0
USB1
Chassis Intrusion
A Chassis Intrusion header is lo-
cated at JL1. Attach the appropri-
ate cable to inform you of a chas-
sis intrusion.
GLAN1
®
S
UPER X6DH8-XG2
GLAN2
D
IM
M
2
B
(B
a
n
k
2
)
D
IM
M
2
A
(B
a
n
k
2)
D
IM
M
3
B
(B
a
n
k
3
)
D
IM
M
3
A
(B
an
k
3
)
D
IM
M
4
B
(B
a
n
k
4
)
D
IM
M
4
A
(B
an
k
4
)
D
IM
M
1A
(B
a
n
k
1
)
D
IM
M
1
B
(B
a
n
k
1
)
Fan1
8-pin
PWR
PWR
SMBus
CPU
Fan1
JF1
FP Control
J
D
1
SPK
PW LED
J
P
1
5
Fan2
OH
3rd PS PWR Fault Detect
CPU Fan2
Fan3
CH Intru
JL1
WD Enable
IPMI
IDE1
IDE2
Floppy
BIOS
J
1
8
JPA1
Ultra 320
SCSI CH A
Ultra 320
S
C
S
I C
H
B
Fan4
7902
CTRL
SATA0
SATA1
USB2/3
SMBUS
Buzzer
PCI-X 1 100 MHz ZCR
PCI-X 2 100 MHz
PCI-X #3 133 MHz
WOR
Battery
JPL1
GLAN
CTLR
RAGE-X
82546
GLAN
Enable
PCI-X #5 133MHz
X8 PCI-Epx #6
S
u
p
e
r
I/O
(North
Bridge)
JPG1
VGA
C
O
M
1
U
S
B
0
/1
KB/
Mouse
Fan5
Fan6
ATX PWR
4-Pin
PW
R
JP16
24-Pin
Force PWR ON
VGA
Enable
Fan7
J24
JP12
R
e
b
o
o
t
O
p
t
io
n
JP14
JP13
Fan8
SCSI
CPU 1
CPU 2
A
la
rm
R
e
s
e
t
SCSI
Enable
PXH
PCI-X #4 133MHz
COM2
WOL
USB4
PWR
Fault
LE1
PW LED
JPA2
JPA3
DA1
D
A
2
ICH5R
PXH
Lindenhurst
Clear
CMOS
C
H
B
S
C
S
I L
E
D
C
H
A
S
C
S
I L
E
D
(South
Bridge)
E
7
5
20
8
2
8
01
E
R
S
C
S
I C
H
A
T
e
rm
S
C
S
I C
H
B
T
e
rm
USB 0/1
Chassis
Intrusion