Data Sheet

PCF8563_5 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 05 — 17 July 2007 15 of 32
NXP Semiconductors
PCF8563
Real time clock/calendar
8.5.2 Clock/calendar read/write cycles
The I
2
C-bus configuration for the different PCF8563 read and write cycles is shown in
Figure 14, Figure 15 and Figure 16. The word address is a 4-bit value that defines which
register is to be accessed next. The upper four bits of the word address are not used.
Fig 14. Master transmits to slave receiver (write mode)
S 0ASLAVE ADDRESS WORD ADDRESS A ADATA P
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
auto increment
memory word address
mbd822
n bytes
Fig 15. Master reads after setting word address (write word address; read data)
S
0ASLAVE ADDRESS WORD ADDRESS A ASLAVE ADDRESS
acknowledgement
from slave
acknowledgement
from slave
acknowledgement
from slave
R/W
acknowledgement
from master
ADATA
auto increment
memory word address
001aag133
P
no acknowledgement
from master
1DATA
auto increment
memory word address
last byte
R/W
S1
n bytes
at this moment master transmitter
becomes master receiver and
PCA8563 slave receiver
becomes slave transmitter
Fig 16. Master reads slave immediately after first byte (read mode)
S
1A
SLAVE ADDRESS DATA
A1DATA
acknowledgement
from slave
acknowledgement
from master
no acknowledgement
from master
R/W
auto increment
word address
mgl665
auto increment
word address
n bytes last byte
P