User's Manual

6 Pinout
6.1 FPGA Pin allocation by bank
Bank I/O Vr* QDR2 SHB CP SLB GB Other Total
1 48 0
2 48 0 8xConfig 8
3 16 0
Clocks & DLL
control
2
4 16 0
Clocks &
Reset &
Switches
13
5 64 4
Bank C Data +
Control
64
6 64 4
Bank B Data +
Control
64
7 64 6 SLB LVTTL 13 Control
PXI, TTL,
INTs, LEDs,
Misc.
64
8 64 6
32 Data &
31 Address &
1 Control
64
9 64 4
Bank D Data &
Control
64
10 64 4
Bank A Data &
Control
64
11 64 6 1xSHB 2xCP 64
12 64 6 1xSHB 2xCP 64
13 64 6
16 Diff Data &
4 Diff Clocks
46
14 64 6
16 Diff Data &
4 Diff Clocks
46
Vr* = Vrp + Vrn + Vref
Table 13: Pin allocation by Bank
6.2 SHB
SUNDANCE SHB specification
6.3 SLB
SUNDANCE SLB specification
User Manual SMT348 Last Edited: 29/02/2008 17:52:00