User's Manual

4.2.9 Sundance High speed Bus
2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word.
They allow interfacing to other Sundance modules providing that you implement an SHB
interface in the FPGA. (See 2.1)
The SHB interface is available in Sundance SMT6500 support package. Either two 16-bit, or 1
32-bit interface can be implemented per connector.
They allow interfacing to the outside world by implementing your own interface in the FPGA.
The FPGA IO banks hosting the SHB signals are powered using Vcco = 3.3V.
4.2.10 Sundance Low voltage Bus
This bus is present on the LX160 version of the module only.
This is an LVDS bus comprising data (2 x 16 bit buses, I & Q), clock, and control signals.
They allow interfacing to Sundance mezzanine modules providing that you implement an SLB
interface in the FPGA. (See 2.1)
They allow interfacing to the outside world by implementing your own LVDS interface in the
FPGA.
All LVDS data pins (both I and Q) are connected to a 2.5/3.3V powered FPGA banks (link
selectable by jumper JP3).
The FPGA LVDS DIFF_TERM standard should be used instead of the DCI terminations when
LVDS standard is selected.
DCI terminations are only available when a 2.5v standard is selected.
The LVDS Clock signals are also in these banks.
All LVTTL signals are connected to a 3.3V powered FPGA bank.
User Manual SMT348 Page 15 of 29 Last Edited: 29/02/2008 17:52:00