User's Manual

4.2.6 FPGA Reset Scheme
The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary
TIM connector pin 30. (See TI TIM specification & User’s guide).
This signal goes to the CPLD and the FPGA.
Nevertheless as a general rule for good practice, the FPGA should not use this reset but should
use the reset signal generated by the CPLD.
The CPLD provides another signal called FPGAResetn that offers a better Reset control over
the FPGA.
At power up or on reception of a low TIM global Reset pulse, the CPLD drives the
FPGAResetn signal low and keeps it low.
This is used to keep the FPGA design in reset.
A new FPGA configuration bitstream can then be downloaded.
When the ENDKEY has been received, the CPLD drives FPGAResetn high.
Use FPGAResetn for the Global Reset signal of your FPGA
designs.
In this manner, you can control your FPGA design Reset activity and you will also avoid
possible conflicts on ComPort 3 if your FPGA design implements it.
(Comport3 is a communication resource shared by the CPLD and the FPGA. But only 1 entity
is allowed to use it at a time).
If you implement comport 3 in the FPGA you have to use
Fpgaresetn generated by the CPLD, as the comport is shared
between the two.
The Reset control is operated by the CPLD line FPGAResetn.
The following diagram shows the CPLD states after Reset.
User Manual SMT348 Page 12 of 29 Last Edited: 29/02/2008 17:52:00