Sundance Multiprocessor Technology Limited Form : QCF42 Date : 6 July 2006 User Manual Unit / Module Description: User Manual Unit / Module Number: SMT348 Document Issue Number: Issue Date: Original Author: E.P User Manual Sundance Multiprocessor Technology Ltd, Chiltern House, Waterside, Chesham, Bucks. HP5 1PS. This document is the property of Sundance and may not be copied nor communicated to a third party without prior written permission.
Revision History Issue Changes Made Date Initials 1.0.0 First release 06/11/06 E.P 1.0.1 Minor inconsistency about comports removed from block Diagram 26/02/07 E.P 1.0.2 Clarification about the elements in the JTAG chain 15/11/07 E.P 1.0.3 Updated JTAG header information. Wrong marking of position. 29/02/08 E.
Table of Contents 1 Introduction ................................................................................................................ 6 2 Related Documents ..................................................................................................... 7 2.1 Referenced Documents .............................................................................................7 2.2 Applicable Documents .........................................................................................
7 Qualification Requirements ......................................................................................25 7.1 Qualification Tests..................................................................................................25 7.1.1 Meet Sundance standard specifications............................................................25 7.1.2 Speed qualification tests ....................................................................................26 7.1.3 Integration qualification tests ....
Table of Figures Figure 1: Block Diagram ........................................................................................................9 Figure 2: CPLD state machine.............................................................................................13 Figure 3: FPGA connections to Bank1 of QDRII.................................................................14 Figure 4: Top View...............................................................................................................
1 Introduction The SMT348 is an FPGA TIM module designed to be integrated in modular systems. It is designed to connect to the huge range of other TIM modules and carriers developed by Sundance. Sundance modular solutions provide flexible and upgradeable systems. The SMT348 is a TIM module aimed at completing the range of Sundance Virtex4 modules like SMT368, SMT362, SMT339.
2 Related Documents 2.1 Referenced Documents SUNDANCE SDB specification. SUNDANCE SHB specification SUNDANCE SLB specification Samsung QDRII Datasheet Spansion S29GLXXXN flash 2.2 Applicable Documents TI TIM specification & user’s guide.
3 Acronyms, Abbreviations and Definitions 3.1 Acronyms and Abbreviations 3.2 TIM Texas Instruments Module TI© DSP Texas Instrument Digital Signal Processor Xilinx© FPGA Xilinx© Field Programmable Gate Array. QDR Quad Data Rate CP ComPort. Communication interface SDB Sundance Digital Bus. Communication interface SHB Sundance High-Speed Bus. Communication interface Definitions DSP Module Typically a TIM module hosting a TI DSP and, a Xilinx FPGA.
4 Functional Description This module conforms to the TIM standard (Texas Instrument Module, See TI TIM specification & user’s guide) for single width modules. It sits on a carrier board. The carrier board provides power (5V, 3.3V, +/-12V), ground, communication links (Comport links) between all the modules fitted and a pathway to the host, for a non stand-alone system. The SMT348 requires a 3.
4.2 Module Description • Block1 and Block6 Xilinx Virtex 4 XC4VSX55/LX160 and configuration scheme. • Block2: QDR2 SRAM memory. • Block3: IO connectors for general purpose or dedicated interfaces. • Block4: 50MHz or 200MHz local clocks, and external clock input. • Block5: LEDs for development and in-use monitoring and general purpose use. 4.2.1 FPGA Xilinx Virtex 4 XC4VSX55FF1148 or XC4VLX160FF1148 FPGA. This device is packaged in a 1148-pin BGA package. 4.2.
4.2.5 FPGA Configuration schemes Different schemes are available to provide maximum flexibility in systems where the SMT348 is involved: The FPGA configuration bitstream source is • On Comport 3: The CPLD is connected to the Comport 3 link of the SMT348 TIM connector. (See block1). A switch is used to select Comport 3 as the link that will be used to receive the bitstream. The CPLD allows for FPGA configuration in slave SelectMAP mode. • Using the on-board Flash memory.
4.2.6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary TIM connector pin 30. (See TI TIM specification & User’s guide). This signal goes to the CPLD and the FPGA. Nevertheless as a general rule for good practice, the FPGA should not use this reset but should use the reset signal generated by the CPLD. The CPLD provides another signal called FPGAResetn that offers a better Reset control over the FPGA.
Figure 2: CPLD state machine 4.2.7 FPGA Bitstream formatting If you generated you FPGA bitstream using Diamond FPGA, you do not need any other handling. The .app file created can be used as is to configure the FPGA. If you used Xilinx ISE and created a .bit file, you need to use the Sundance executable “Getrawdata.exe” provided for free in the SMT6001 package. Please read the SMT6001 help file at chapter: “Saving FPGA configuration data to file”.
4.2.8 QDR2 SRAM Up to 4 Mbytes of QDR2 SRAM per bank. The memory is available as 4 independent banks. The QDR2 memory runs at 250MHz. Each bank is fully independent with separate address, control and data busses and arranged as follows: Figure 3: FPGA connections to Bank1 of QDRII The devices used are Samsung K7R321884M. Alternative part numbers, fully compatible can be fitted depending on availability at time of order.
4.2.9 Sundance High speed Bus 2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word. They allow interfacing to other Sundance modules providing that you implement an SHB interface in the FPGA. (See 2.1) The SHB interface is available in Sundance SMT6500 support package. Either two 16-bit, or 1 32-bit interface can be implemented per connector. They allow interfacing to the outside world by implementing your own interface in the FPGA.
4.2.11 TIM Connectors TIM connectors provide 4 communication links (Comports) and a Global Bus to the FPGA. The comports which are available on the SMT348 are CP0, CP1, CP3, and CP4. They allow interfacing to Sundance TIM modules or to a Host PC providing that you implement a Comport Interface inside the FPGA. (See 2.1) The Comport interface is available in Sundance SMT6500 support package. The FPGA io banks hosting the Comport signals are powered using Vcco = 3.3v.
4.2.13 Clocking scheme The SMT348 module contains a 50MHz LVTTL clock, a 200MHz clock, and a connector for an external LVTTL clock input/output. 50 MHz LVTTL oscillator: Main system clock. Clocks the CPLD and the FPGA. Can be input in a DCM. 200MHz LVTTL oscillator: QDRII clock. Can also be used as a main FPGA clock. Can be input in a DCM. An external clock input is provided to the Virtex 4 FPGA via an MMCX connector. This connector is NOT fitted by default or if a mezzanine is required.
As a result, check your main power supply ratings. If your system is likely to reach 25W per power rail we advice that you provide extra power to the carrier board using an external power supply. Device Name Quantity Voltage(V) Current(mA) Power(W) Source 3.3v power supply V33 1 3.3 7600 25 PCI specifications Table 4: Total available power. Device Nam e Quantit y Voltage(V) Curren t(mA) Power(W) Source XC4VLX160FF1148-11 Vccint=1.2v Vfpg a 1 1.2 1.805 2.
Device Name Quantity Voltage (V) Current(mA ) Power(W) Source Samsung QDR II burst 4 (18-bit interface) V18 4 1.8 800 5.76 Samsung QDRII (25), datasheet rev1.1 p.9 ML6554CU DC/DC converter V18 1 1.8 0.01 0.018 Fairchild ML6554CU (obsolete) Coolrunner XC2C256CP132 V18 1 1.8 0.55 0.00099 Ise 8.2.03i Xpower software version: I.34 XC4VLX160FF1148-11 HSTL II V18 1 1.8 829 1.497 Virtex-4 power estimator Total power consumed V18 HSTL power plane (1.
Device Name Quantity Voltage(V) Current(mA) Power(W) Source QDRII Vref VR09 8 0.9 0 0 Samsung QDRII (25), datasheet rev1.1 p.9 XC4VLX160FF1148-11 HSTL Vref VR09 16 0.9 0.01 0.000144 DS302 (v1.17) table 3 p.3 Total power consumed VR09 HSTL Vref plane (0.9v) capacity VR09 0.000144 1 0.9 3 0.0027 Excess power Fairchild ML6554CU (obsolete) 0.002556 Table 9: Power budget on QDRII and FPGA 0.9v reference voltage.
Details: Coolrunner XC2C256-6-CP132 power requirements based on design: Macrocells Function Block Pterms Used Registers Used Pins Used Used Inputs Used 218/256 (86%) 531/896 (60%) 190/256 (75%) 69/106 (66%) 445/640 (70%) Table 11: Coolrunner II resources summary. Signal Type Required Input 8 Output 40 Bidirectional 20 GCK 1 GTS 0 GSR 0 Mapped 8 40 20 1 0 0 Pin Type I/O GCK/IO GTS/IO GSR/IO CDR/IO DGE/IO Used 65 3 0 1 0 0 Total 96 3 4 1 1 1 Table 12:Coolrunner II pin resources.
5 Footprint 5.
5.
6 Pinout 6.1 FPGA Pin allocation by bank Bank I/O Vr* 1 2 48 48 0 0 3 16 0 4 16 0 5 64 4 6 64 4 7 64 6 8 64 6 9 64 4 10 64 4 11 12 64 64 6 6 13 64 6 14 64 6 QDR2 SHB CP SLB GB Other Total 8xConfig 8 Clocks & DLL control 2 Clocks & Reset & Switches Bank C Data + Control Bank B Data + Control 13 64 64 SLB LVTTL Bank D Data & Control Bank A Data & Control PXI, TTL, 13 Control INTs, LEDs, 64 Misc.
6.4 JTAG TDO 4 TCK 3 TDI 5 GND 2 TMS 6 3.3V 1 JP1 Figure 6: JTAG Connector, top view 7 Qualification Requirements 7.1 Qualification Tests 7.1.1 Meet Sundance standard specifications • Meet the TIM standard specifications • Meet the SLB specifications (LVDS standard). • Meet the SHB specifications.
7.1.2 Speed qualification tests • 7.1.3 8 QDR2 memory accesses at 250MHz. Integration qualification tests • Must work on ALL Sundance platforms as a root TIM module or as part of a network of TIMs on carriers. • Must be able to work stand-alone.
9 Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +5V +3.
10 Safety This module presents no hazard to the user when in normal use.
11 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables. Short circuiting any output to ground does not cause the host PC system to lock up or reboot.
