Datasheet

Sun Microsystems, Inc.
one another. Memory transactions must propagate through the Northbridge chip fabric which also carries I/O traffic. This can pres-
ent a bottleneck at the front-side bus that greatly reduces productivity and performance potential. In the AMD Direct Connect Archi-
tecture, each CPU has its own integrated memory controller, fostering more linear, symmetrical multiprocessing and optimized
memory performance. This direct connection to the memory controller significantly reduces the memory latency seen by the proces-
sor. Latency continues to drop as the processor frequency scales.
Additionally, hardware and software memory pre-fetching mechanisms can further reduce the effective memory latency seen by the
processor. This reduction in memory latency, coupled with the additional increase in memory bandwidth enabled by a directly con-
nected processor, presents a critical advantage as it greatly enhances system performance across all application segments.
I/O Expansion Capability to High Speed Industry Buses
The traditional Northbridge/Southbridge architecture is not intended to support more than two core-logic elements. Adding addi-
tional high speed functionality, such as Gigabit Ethernet, PCI-Express, or the InfiniBand architecture, can impact system performance
and cost. HyperTransport technology provides system designers with a high speed interconnect between system components. These
elements connect in a building block fashion to achieve a platform with specific feature set and performance objectives.
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