User's Manual

SDC-SSD40NBT
User’s Manual, version 4.1
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Integration Considerations
The following Wi-Fi and Bluetooth information should be taken into consideration when integrating the
SSD40NBT.
Wi-Fi
Series resistors are recommended in all six SDIO lines (27-56 ohms typically):
 SDIO_CLK
 SDIO_CMD
 SDIO_DATA_0
 SDIO_DATA_1
 SDIO_DATA_2
 SDIO_DATA_3
Note: Although these values may vary with the properties of your host interface and the PCB, they are a
reasonable starting point.
Note: The series resistors in the SDIO bus provide several design benefits:
- If a host controller has too high of a drive strength, then bus ringing may result. Series resistors can
reduce this ringing on the I/O lines.
- Adding 27-56 ohms of series resistance on the SDIO bus will reduce sharp transitional edges, which
may reduce EMI.
- Having the series resistors in the PCB layout allows for design flexibility; If they are later found to be
unnecessary, zero (0) ohm jumpers may be used in their place
The following are also recommended:
 47 K ohm pull-ups on the CMD line and four data lines: SDIO_CMD, SDIO_DATA_0, SDIO_DATA_1,
SDIO_DATA_2, SDIO_DATA_3
Note: No pull-up is required on the CLK line.
Note: Make sure to apply the proper voltage on the VDDIO input to the SiP to match the signaling voltage
of the SDIO host interface (1.8V or 3.3V typically, but it can be anything in between these values).
Note: The SDIO host must wait a minimum of 110 ms before initiating access to the SDC-SSD40NBT after
VDD ramps up and settles.
Bluetooth
When the BT radio is not being used, the BT_RST_L line may be held low to save some overall current
consumption.
When the BT radio is being used, the BT_RST_L line may be left floating (because there is a 10 K ohm pull-up
resistor on this line inside the SSD40NBT SiP).
If the BT_RST_L is coming from a GPIO from the host processor, then it may be easier (although not
necessary) to assert a HIGH on this line, rather than making it an input.