User's Manual

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SDC-SSD40NBT

User’s Manual, version 4.1

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www.lairdtech.com/wireless

20

Laird Technologies

Pin

Number

Pin

Name

I/O

Voltage

Reference

Description

See “Electrical Considerations” for the

recommended SYS_RST_L circuitry

36

CHIP_PWD_L

I

VDDIO

Powers down both the BT and WLAN radios,

active low (see Note).

37

BT_RST_L

I

VDDIO

Resets the Bluetooth radio, active low. Must

be asserted when power is first applied to the

radio, then released before

any transaction can start.

Note: See “Integration Considerations” for

additional integration information.

38

SDIO_DATA_0

I/O

VDDIO

SDIO Data 0

Note: See “Integration Considerations” for

additional integration information.

39

GND

-

Ground

40

SDIO_CLK

I

VDDIO

SDIO Clock (25MHz max)

Note: See “Integration Considerations” for

additional integration information.

41

GND

-

Ground

42

SDIO_DATA_1

I/O

VDDIO

SDIO Data 1

Note: See

“Integration

Considerations” for

additional integration

information.

43

SDIO_DATA_3

I/O

VDDIO

SDIO Data 3

44

SDIO_DATA_2

I/O

VDDIO

SDIO Data 2

45

SDIO_CMD

I/O

VDDIO

SDIO Command

46

GND

-

Ground

47

CLK_32K

I

32k Ext Sleep Clock

Note: The Broadcom BCM4329 (the core of the

SSD40NBT) does not have an internal sleep clock.

The SSD40NBT requires an external 32K sleep

clock. Summit recommends the ECS-327KE or

similar product.

48

RSVD

I

VDDIO

Reserved, No Connect

49

RSVD

O

VDDIO

Reserved, No Connect

50

RSVD

I/O

VDDIO

Reserved, No Connect

51

RSVD

I/O

VDDIO

Reserved for GPIO. Leave open (float).

52

RSVD

I/O

VDDIO

Reserved, No Connect

53

RSVD

I/O

VDDIO

Reserved for GPIO. No Connect.

54

RSVD

I/O

VDDIO

Reserved for GPIO. No Connect.

55

RSVD

I/O

VDDIO

Reserved for GPIO. No Connect.

56

RSVD

I/O

VDDIO

Reserved for GPIO. No Connect.

Note Regarding SYS_RST_L and CHIP_PWD_L:

Simply releasing SYS_RST_L and CHIP_PWD_L does not guarantee that the BCM4329 chip in the

SSD40NBT module comes out of reset. Ensure that both VDD and VDDIO have been applied to the

SSD40NBT for at least 110 ms before attempting to initiate SDIO communications. A slightly longer

delay is better (safer).