User's Manual

SDC-SSD40NBT
User’s Manual, version 4.1
Americas: [phone] Option 3
Europe: [phone]
Hong Kong: [phone] x026
www.lairdtech.com/wireless
16
Laird Technologies
Long Frame Sync, Slave Mode
Figure 6: Long Frame Sync, Slave Mode
Table 8: Long Frame Sync, Slave Mode
Reference
Description
Min.
Typ.
Max.
Unit
1
PCM bit clock frequency
128
-
2048
kHz
2
PCM bit clock high time
209
-
-
ns
3
PCM bit clock low time
209
-
-
ns
4
Setup time for BT_PCM_SYNC before
falling edge of BT_PCM_CLK during
first bit time
50
-
-
ns
5
Hold time for BT_PCM_SYNC after
falling edge of BT_PCM_CLK during
second bit period.
Note: BT_PCM_SYNC may go low any
time from second bit period to last bit
period.
10
-
-
ns
6
Delay from rising edge of BT_PCM_CLK
or BT_PCM_SYNC (whichever is later)
to data valid for first bit on
BT_PCM_OUT
-
-
50
ns
7
Hold time of BT_PCM_OUT after
BT_PCM_CLK falling edge
-
-
175
ns
8
Setup time for BT_PCM_IN before
BT_PCM_CLK falling edge
50
-
-
ns
9
Hold time for BT_PCM_IN after
BT_PCM_CLK falling edge
10
-
-
ns
10
Delay from falling edge of
BT_PCM_CLK or BT_PCM_SYNC
(whichever is later) during last bit in
slot to BT_PCM_OUT becoming high
impedance
-
-
100