Datasheet

VNQ5050K-E Electrical specifications
Doc ID 10864 Rev 7 11/31
t
POL
Delay between input
falling edge and status
rising edge in open-
load condition
I
OUT
= 0A (See Figure 4.) 200 500 1000 μs
V
OL
Open-load off-state
voltage detection
threshold
V
IN
= 0V, 8V<V
CC
<16V
(See Figure 23.)
24V
t
DSTKON
Output short circuit to
V
cc
detection delay at
turn-off
(See Figure 4.)180t
POL
μs
Table 11. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level 0.9 V
I
IL
Low level input current V
IN
= 0.9V 1 μA
V
IH
Input high level 2.1 V
I
IH
High level input current V
IN
= 2.1V 10 μA
V
I(hyst)
Input hysteresis
voltage
0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level
voltage
0.9 V
I
SDL
Low level STAT_DIS
current
V
SD
=0.9V 1 μA
V
SDH
STAT_DIS high level
voltage
2.1 V
I
SDH
High level STAT_DIS
current
V
SD
=2.1V 10 μA
V
SD(hyst)
STAT_DIS hysteresis
voltage
0.25 V
V
SDCL
STAT_DIS clamp
voltage
I
SD
=1mA
I
SD
=-1mA
5.5
-0.7
7V
V
Table 10. Open-load detection (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit