VNL5160N3-E VNL5160S5-E OMNIFET III fully protected low-side driver Datasheet - production data Description 2 1 2 3 SO-8 SOT-223 Features Type Vclamp RDS(on) ID 41 V 160 mΩ 3.5 A VNL5160N3-E VNL5160S5-E The VNL5160N3-E and VNL5160S5-E are monolithic devices, made using STMicroelectronics® VIPower® Technology, intended for driving resistive or inductive loads with one side connected to the battery. Built-in thermal shutdown protects the chip from overtemperature and short circuit.
Contents VNL5160N3-E, VNL5160S5--E Contents 1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Electrical characteristics . . . . . . . . . .
VNL5160N3-E, VNL5160S5--E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures VNL5160N3-E, VNL5160S5--E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. 4/27 VNL5160N3-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 VNL5160S5-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VNL5160N3-E, VNL5160S5--E 1 Block diagrams and pins configurations Block diagrams and pins configurations Figure 1. VNL5160N3-E block diagram $2!). /2*,& &RQWURO 'LDJQRVWLF &XUUHQW /LPLWDWLRQ ,1387 3RZHU &ODPS '5,9(5 29(57(03(5$785( 3527(&7,21 29(5/2$' 3527(&7,21 $&7,9( 32:(5 /,0,7$7,21 *1' ("1($'5 Figure 2. VNL5160S5-E block diagram $2!).
Block diagrams and pins configurations VNL5160N3-E, VNL5160S5--E Table 2. Pin function Name Function INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state(1) DRAIN PowerMOS drain SOURCE PowerMOS source and ground reference for the control section SUPPLY VOLTAGE Supply voltage connected to the signal part (5V) Open drain digital diagnostic pin(2) STATUS 1. Internally connected to Vsupply in the VNL5160N3-E. 2. Valid for VNL5160S5-E only. Figure 3.
VNL5160N3-E, VNL5160S5--E Block diagrams and pins configurations Figure 5. Configuration diagrams (top view) SOT-223 SO-8 Table 3. Suggested connections for unused and not connected pins Connection/pin Status N.C.
Absolute maximum rating 2 VNL5160N3-E, VNL5160S5--E Absolute maximum rating Stressing the device above the rating listed in Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.1 Absolute maximum ratings Table 4.
VNL5160N3-E, VNL5160S5--E 2.2 Absolute maximum rating Thermal data Table 5. Thermal data Maximum value Symbol Rthj-amb Parameter Thermal resistance junction-ambient Unit SOT-223 SO-8 146.8(1) 103.1 °C/W 1. When mounted on a standard single-sided FR4 board with 0.
Electrical characteristics 3 VNL5160N3-E, VNL5160S5--E Electrical characteristics Values specified in this section are for VIN = Vsupply = 4.5 V to 5.5 V, -40 °C < Tj < 150 °C, unless otherwise stated. Table 6. PowerMOS section Symbol Vsupply RON Parameter Test conditions Min. Typ. Max. Unit 3.5 5 5.
VNL5160N3-E, VNL5160S5--E Electrical characteristics Table 9. Status pin(1) (continued) Symbol Parameter Test conditions CSTAT Status pin input capacitance VSTCL Status clamp voltage Min. Typ. Max. Unit 100 pF 7 V Normal operation; VSTAT = 5 V ISTAT = 1 mA 5.5 ISTAT = -1 mA -0.7 V 1. Valid for VNL5160S5-E option. Table 10.
Electrical characteristics VNL5160N3-E, VNL5160S5--E Table 13. Switching characteristics (VCC = 13 V(1)) SOT-223(2) Symbol Parameter SO-8 Unit Test conditions Min. Typ. Max Min. Typ. Max. td(ON) Turn-on delay time RL = 13Ω, VCC = 13V(3) 8.9 8.9 µs td(OFF) Turn-off delay time RL = 13Ω, VCC = 13V 13.2 13.2 µs tr Rise time RL = 13Ω, VCC = 13V 14.1 14.1 µs tf Fall time RL = 13Ω, VCC = 13V 11.5 11.5 µs WON Switching energy losses at turn-on RL = 13Ω, VCC = 13V 34.3 34.
VNL5160N3-E, VNL5160S5--E Electrical characteristics Table 15. Truth table (1) Conditions INPUT DRAIN STATUS Normal operation L H H L H H Current limitation L H H X H H Overtemperature L H H H H L Undervoltage L H H H X X Output voltage < VOL L H L L L H 1. Valid for VNL5160S5-E option Figure 6.
Application information 4 VNL5160N3-E, VNL5160S5--E Application information Figure 7. VNL5160N3-E application schematic 9FF 9 5/ 0LFUR&RQWUROOHU ,1387 '5$,1 5SURW 6285&( ("1( $'5 Figure 8.
VNL5160N3-E, VNL5160S5--E 4.1 Application information MCU I/O protection ST suggests to insert a resistor (Rprot) in line to prevent the µC I/O pins from latching up(a). The value of these resistors is a compromise between the leakage current of µC and the current required by the LSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: 0.7/Ilatchup ≤ Rprot ≤ (VOHµC-VIH) / IIHmax Calculation example: For the following conditions: Ilatchup ≥ 20mA VOHµC ≥ 4.5V 35Ω ≤ Rprot ≤100kΩ.
Application information VNL5160N3-E, VNL5160S5--E Figure 9.
VNL5160N3-E, VNL5160S5--E Package and PC board thermal data 5 Package and PC board thermal data 5.1 SOT-223 thermal data Figure 10. SOT-223 PC board GAPGCFT00530 Note: Layout condition of Rth and Zth measurements (PCB FR4 area = 30 mm x 30 mm,PCB thickness = 2 mm, Cu thickness=35 µm, Copper areas: from minimum pad layout to 0.8 cm2). Figure 11. SOT-223 Rthj-amb vs PCB copper area in open box free air condition RTHjamb 160 footprint 150 RTHj_amb(°C/W) 140 130 120 110 100 90 80 70 60 0 0.5 1 1.
Package and PC board thermal data VNL5160N3-E, VNL5160S5--E Figure 12. SOT-223 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Footprint 2 cm2 100 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 1: pulse calculation formula Z TH δ = R TH ⋅δ+Z THtp (1 – δ) where δ = tP/T Figure 13. SOT-223 thermal fitting model 1.
VNL5160N3-E, VNL5160S5--E Package and PC board thermal data Table 16. SOT-223 thermal parameter 5.2 Area/island (cm2) FP R1 (°C/W) 1.4 R2 (°C/W) 1.8 R3 (°C/W) 4.5 R4 (°C/W) 24 R5 (°C/W) 0.1 R6 (°C/W) 115 C1 (W·s/°C) 0.0003 C2 (W·s/°C) 0.002 C3 (W·s/°C) 0.03 C4 (W·s/°C) 0.16 C5 (W·s/°C) 1000 C6 (W·s/°C) 0.4 2 45 2 SO-8 thermal data Figure 14.
Package and PC board thermal data VNL5160N3-E, VNL5160S5--E Figure 15. SO-8 Rthj-amb vs PCB copper area in open box free air condition RTHjamb 115 RTHj_amb(°C/W) 105 footprint 95 85 75 65 0 0.5 1 1.5 2 2.5 PCB Cu heatsink area (cm^2) - (refer to PCB layout) Figure 16. SO-8 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Footprint 100 2 cm2 10 1 0.1 0.0001 0.001 0.01 0.
VNL5160N3-E, VNL5160S5--E Package and PC board thermal data Figure 17. SO-8 thermal fitting model 1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 17. SO-8 thermal parameter 2 Area/island (cm ) 0.07 R1 (°C/W) 1.4 R2 (°C/W) 3.2 R3 (°C/W) 3.5 R4 (°C/W) 21 R5 (°C/W) 16 R6 (°C/W) 58 C1 (W·s/°C) 0.0008 C2 (W·s/°C) 0.0032 C3 (W·s/°C) 0.
Package and packing information VNL5160N3-E, VNL5160S5--E 6 Package and packing information 6.1 ECOPACK® packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.2 SOT-223 mechanical data Figure 18.
VNL5160N3-E, VNL5160S5--E 6.3 Package and packing information SO8 mechanical data Figure 19. SO8 mechanical data & package outline mm inch DIM. MIN. TYP. A MAX. MIN. TYP. MAX. 1.750 0.0689 A1 0.100 0.250 0.0039 0.0098 A2 1.250 0.0492 b 0.280 0.480 0.0110 0.0189 c 0.170 0.230 0.0067 0.0091 D (1) 4.800 4.900 5.000 0.1890 0.1929 0.1969 E 5.800 6.000 6.200 0.2283 0.2362 0.2441 E1(2) 3.800 3.900 4.000 0.1496 0.1535 0.1575 e 1.270 0.0500 h 0.250 0.500 0.0098 L 0.
Package and packing information 6.4 VNL5160N3-E, VNL5160S5--E SOT-223 packing information The devices can be packed in tube or tape and reel shipments (see the Table 1: Device summary). Figure 20. SOT-223 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb.
VNL5160N3-E, VNL5160S5--E 6.5 Package and packing information SO8 packing information Figure 21. SO-8 tube shipment (no suffix) B C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) A 100 2000 532 3.2 6 0.6 Figure 22. SO-8 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm.
Revision history 7 VNL5160N3-E, VNL5160S5--E Revision history Table 18. Document revision history Date Revision 17-Nov-2009 1 Initial release. 20-Feb-2012 2 Update the entire document in ST template. Update Section : Features in cover page. 3 Table 9: Status pin: – -ID: updated value Table 9: Status pin: – IISS: updated max value Table 13: Switching characteristics (VCC = 13 V): – IS: updated max value Updated Figure 8: VNL5160S5-E application schematic Updated Section 4.
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