Datasheet

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This is information on a product in full production.

December 2013 DocID15917 Rev 6 1/33

VNL5050N3-E

VNL5050S5-E

OMNIFET III

fully protected low-side driver

Datasheet

production data

Features

• Automotive qualified

• Drain current: 19 A

• ESD protection

• Overvoltage clamp

• Thermal shutdown

• Current and power limitation

• Very low standby current

• Very low electromagnetic susceptibility

• Compliant with European directive 2002/95/EC

• Open drain status output (VNL5050S5-E only)

Description

The VNL5050N3-E and VNL5050S5-E are

monolithic devices made using

STMicroelectronics VIPower

Technology,

intended for driving resistive or inductive loads

with one side connected to the battery.

Built-in thermal shutdown protects the chip from

overtemperature and short-circuit. Output current

limitation protects the devices in an overload

condition. In case of long duration overload, the

devices limit the dissipated power to a safe level

up to thermal shutdown intervention.Thermal

shutdown, with automatic restart, allows the

devices to recover normal operation as soon as a

fault condition disappears. Fast demagnetization

of inductive loads is achieved at turn-off.

Type V

clamp

DS(on)

VNL5050N3-E

41 V 50 mΩ 19 A

VNL5050S5-E

SOT-223

SO-8

Table 1. Devices summary

Package

Order codes

Tube Tape and reel

SOT-223 VNL5050N3-E VNL5050N3TR-E

SO-8 VNL5050S5-E VNL5050S5TR-E

www.st.com

Summary of content (33 pages)

PAGE 1
VNL5050N3-E VNL5050S5-E OMNIFET III fully protected low-side driver Datasheet - production data Description 2 1 2 The VNL5050N3-E and VNL5050S5-E are monolithic devices made using STMicroelectronics VIPower® Technology, intended for driving resistive or inductive loads with one side connected to the battery. 3 SOT-223 SO-8 Built-in thermal shutdown protects the chip from overtemperature and short-circuit. Output current limitation protects the devices in an overload condition.
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Contents VNL5050N3-E, VNL5050S5-E Contents 1 Block diagrams and pins configurations . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 4 5 6 2/33 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . .
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VNL5050N3-E, VNL5050S5-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Devices summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures VNL5050N3-E, VNL5050S5-E List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. 4/33 VNL5050N3-E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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VNL5050N3-E, VNL5050S5-E 1 Block diagrams and pins configurations Block diagrams and pins configurations Figure 1. VNL5050N3-E block diagram Drain LOGIC Control & Diagnostic Current Limitation IN Power Clamp DRIVER OVERTEMPERATURE PROTECTION OVERLOAD PROTECTION (ACTIVE POWER LIMITATION) GND Figure 2.
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Block diagrams and pins configurations VNL5050N3-E, VNL5050S5-E Table 2. Pin function Name Function INPUT Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state(1) DRAIN Power MOS drain SOURCE Power MOS source and ground reference for the control section SUPPLY VOLTAGE Supply voltage connected to the signal part (5 V) Open drain digital diagnostic pin(2) STATUS 1. Internally connected to Vsupply in the VNL5050N3-E 2. Valid for VNL5050S5-E only. Figure 3.
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VNL5050N3-E, VNL5050S5-E Block diagrams and pins configurations Figure 5. Configuration diagrams (top view) %3"*/ 4063$& %3"*/ */165 %3"*/ / $ 4063$& 45"564 4063$& */165 %3"*/ 4611-: 70-5"(& 405 40 ("1( $'5 Table 3. Suggested connections for unused and n.c. pins Connection / pin STATUS N.C.
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Absolute maximum rating 2 VNL5050N3-E, VNL5050S5-E Absolute maximum rating Stressing the device above the rating listed in the Table 4 may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.1 Absolute maximum ratings Table 4.
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VNL5050N3-E, VNL5050S5-E 3 Electrical characteristics Electrical characteristics Values specified in this section are for Vsupply = VIN = 4.5 V to 5.5 V, -40 °C < Tj < 150 °C, unless otherwise stated. Table 6. Power MOS section Symbol Vsupply RON Parameter Test conditions Min. Typ. Max. Unit - 3.5 5 5.
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Electrical characteristics VNL5050N3-E, VNL5050S5-E Table 9. Status pin(1) (continued) Symbol VSTCL Parameter Test conditions ISTAT = 1 mA Status clamp voltage Min. Typ. 5.5 Max. Unit 7 V ISTAT = -1 mA -0.7 1. Valid for VNL5050S5-E option Table 10. Logic input(1) Symbol Parameter Test conditions Min. Typ. Max. Unit 0.9 V VIL Low-level input voltage — IIL Low-level input current VIN = 0.9 V 1 µA VIH High-level input voltage — 2.1 V IIH High-level input current VIN = 2.
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VNL5050N3-E, VNL5050S5-E Electrical characteristics Table 13. Switching characteristics(1) SOT-223(2) Symbol Parameter SO-8 Unit Test conditions Min. Typ. Max Min. Typ. Max. td(ON) Turn-on delay time RL = 6.5 Ω, VCC = 13 V(3) — 6 — — 6 — µs td(OFF) Turn-off delay time RL = 6.5 Ω, VCC = 13 V — 20 — — 20 — µs tr Rise time RL = 6.5 Ω, VCC = 13 V — 10 — — 10 — µs tf Fall time RL = 6.
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Electrical characteristics 3.1 VNL5050N3-E, VNL5050S5-E Electrical characteristics curves Figure 6. Source diode forward characteristics Figure 7. Static drain source on-resistance vs.
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VNL5050N3-E, VNL5050S5-E Electrical characteristics Figure 10. Transfer characteristics Figure 11.
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Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 14. Normalized input threshold vs. temperature 9LQWK 9 ,G P$ 7M & 1RWH ,QSXW DQG VXSSO\ SLQV FRQQHFWHG WRJHWKHU ("1( $'5 Table 15. Truth table(1) Conditions INPUT DRAIN STATUS Normal operation L H H L H H Current limitation L H H X H H Overtemperature L H H H H L Undervoltage L H H H X X Output voltage < VOL L H L L L H 1.
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VNL5050N3-E, VNL5050S5-E Electrical characteristics Figure 15. Switching characteristics *% US UG U UE PGG UE PO 7HFO U ("1( $'5 Figure 16.
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Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 17.
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VNL5050N3-E, VNL5050S5-E 3.2 Electrical characteristics MCU I/O protection ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching up(a). The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the LSD I/Os (input levels compatibility) with the latch-up limit of microcontroller I/Os: Equation 1 0 .7 I latchup ≤ R prot ≤ (V OH μ C − V IH ) I IH max Let: • Ilatchup > 20 mA • VOHµC > 4.
PAGE 18
Electrical characteristics VNL5050N3-E, VNL5050S5-E Figure 18. Maximum demagnetization energy 91/ [ 0D[LPXP WXUQ RII FXUUHQW YHUVXV LQGXFWDQFH 91/ [ 6LQJOH 3XOVH 5HSHWLWLYH SXOVH 7MVWDUW & , $ 5HSHWLWLYH SXOVH 7MVWDUW & / P+ 91/ [ 0D[LPXP WXUQ RII (QHUJ\ YHUVXV 7GHPDJ 91/ [ 6LQJOH 3XOVH 5HSHWLWLYH SXOVH 7MVWDUW & 5HSHWLWLYH SXOVH 7MVWDUW & ( >P-@ 7GHPDJ >PV@ ("1( $'5 1. The voltage supply is VCC = 13.
PAGE 19
VNL5050N3-E, VNL5050S5-E Package and PC board thermal data 4 Package and PC board thermal data 4.1 SOT-223 thermal data Figure 19. SOT-223 PC board 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 30 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm, copper areas: from minimum pad lay-out to 0.8 cm2). Figure 20. Rthj-amb vs. PCB copper area in open box free air condition RTHjamb (°C/W) 150 footprint 140 RTHj_amb(°C/W) 130 120 110 100 90 80 70 60 0 0.5 1 1.5 2 2.
PAGE 20
Package and PC board thermal data VNL5050N3-E, VNL5050S5-E Figure 21. SOT-223 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Cu footprint 100 Cu=2 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 2: pulse calculation formula Z THδ = R TH Þδ+Z THtp (1 – δ) where δ = tP/T Figure 22. Thermal fitting model of a LSD in SOT-223 1.
PAGE 21
VNL5050N3-E, VNL5050S5-E Package and PC board thermal data Table 16. Thermal parameters Area/island (cm2) Footprint R1 (°C/W) 0.4 R2 (°C/W) 0.8 R3 (°C/W) 4.5 R4 (°C/W) 24 R5 (°C/W) 0.1 R6 (°C/W) 115 C1 (W.s/°C) 0.00006 C2 (W.s/°C) 0.0005 C3 (W.s/°C) 0.03 C4 (W.s/°C) 0.16 C5 (W.s/°C) 1000 C6 (W.s/°C) 0.
PAGE 22
Package and PC board thermal data 4.2 VNL5050N3-E, VNL5050S5-E SO-8 thermal data Figure 23. SO-8 PC board 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness = 2 mm, Cu thickness = 35 µm (front and back side), Copper areas: from minimum pad lay-out to 2 cm2). Figure 24. Rthj-amb vs. PCB copper area in open box free air condition RTHjamb (°C/W) 105 footprint RTHj_amb(°C/W) 95 85 75 65 0 0.5 1 1.
PAGE 23
VNL5050N3-E, VNL5050S5-E Package and PC board thermal data Figure 25. SO-8 thermal impedance junction ambient single pulse ZTH (°C/W) 1000 Cu=footprint 100 Cu=2 cm2 10 1 0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000 Equation 3: pulse calculation formula Z THδ = R TH Þδ+Z THtp (1 – δ) where δ = tP/T Figure 26. Thermal fitting model of a LSD in SO-8 1.
PAGE 24
Package and PC board thermal data VNL5050N3-E, VNL5050S5-E Table 17. Thermal parameters 24/33 Area/island (cm2) Footprint R1 (°C/W) 0.4 R2 (°C/W) 2.4 R3 (°C/W) 3.5 R4 (°C/W) 21 R5 (°C/W) 16 R6 (°C/W) 58 C1 (W.s/°C) 0.00008 C2 (W.s/°C) 0.0016 C3 (W.s/°C) 0.0075 C4 (W.s/°C) 0.045 C5 (W.s/°C) 0.35 C6 (W.s/°C) 1.
PAGE 25
VNL5050N3-E, VNL5050S5-E Package and packing information 5 Package and packing information 5.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 SOT-223 mechanical data Figure 27.
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Package and packing information VNL5050N3-E, VNL5050S5-E Table 18. SOT-223 mechanical data mm. inch DIM. Min. Typ. A Max. Typ. 1.8 Max. 0.071 B 0.6 0.7 0.85 0.024 0.027 0.033 B1 2.9 3 3.15 0.114 0.118 0.124 c 0.24 0.26 0.35 0.009 0.01 0.014 D 6.3 6.5 6.7 0.248 0.256 0.264 e 2.3 0.09 e1 4.6 0.181 E 3.3 3.5 3.7 0.13 0.138 0.146 H 6.7 7 7.3 0.264 0.276 0.287 V A1 26/33 Min. 10 (max) 0.02 0.1 DocID15917 Rev 6 0.0008 0.
PAGE 27
VNL5050N3-E, VNL5050S5-E 5.3 Package and packing information SO-8 mechanical data Figure 28.
PAGE 28
Package and packing information VNL5050N3-E, VNL5050S5-E Table 19. SO-8 mechanical data Millimeters Symbol Min. Typ. A Max. 1.75 A1 0.10 A2 1.25 b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 0.25 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0° ccc 8° 0.10 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2.
PAGE 29
VNL5050N3-E, VNL5050S5-E 5.4 Package and packing information SOT-223 packing information The devices can be packed in tube or tape and reel shipments (see the Table 1: Devices summary on page 1 ). Figure 29. SOT-223 tape and reel shipment (suffix “TR”) Reel dimensions Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4 Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb.
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Package and packing information 5.5 VNL5050N3-E, VNL5050S5-E SO-8 packing information Figure 30. SO-8 tube shipment (no suffix) B Base q.ty Bulk q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 31. SO-8 tape and reel shipment (suffix “TR”) Reel dimensions Base q.ty Bulk q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm.
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VNL5050N3-E, VNL5050S5-E 6 Revision history Revision history Table 20. Document revision history Date Revision 9-Jan-2008 1 Initial release. 2 Updated corporate template from V2 to V3 Table 3: Suggested connections for unused and n.c. pins – VESD1: updated parameter and value – VESD2: changed value Table 4: Absolute maximum ratings – Rthj-case: deleted max value for SO-8 – Rthj-amb: added max value for both SOT-223 and SO-8 Table 7: Source drain diode – VSD: added typ value Table 8: Input section.
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Revision history VNL5050N3-E, VNL5050S5-E Table 20.
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VNL5050N3-E, VNL5050S5-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.