Datasheet

Functional pin description VNI8200XP
22/40 DocID15234 Rev 6
9.9 Fault indication (FAULT)
The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or
more of the following conditions:
• Channel overtemperature (OVT)
This pin is activated when at least one of the channels is in junction overtemperature.
Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only
when the fault condition is active and is released if the input driving signal is off or after
the OVT protection condition has been removed. This last event occurs if the channel
temperature decreases below the threshold level and the case temperature has not
exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the
junction overtemperature is active (T
J
>T TSD ) and is released after this condition has
been removed (T
J
< T R and T C < T CR ).
• Parity check fail
When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is
detected or counted, CLK rising edges are different by a multiple of 8, the FAULT
pin is
kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid,
the FAULT
pin is kept high.
9.10 Power Good (PG)
The PG terminal is an open drain, that indicates the status of the supply voltage. When V
CC
supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It goes
into a low impedance state when V
CC
falls below the Vsth2 threshold.
In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good
diagnostic is active, it is otherwise cleared.
Figure 7. Power Good diagnostic
9FF
3*
93*+ 93*+
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