Datasheet

Functional pin description VNI8200XP
20/40 DocID15234 Rev 6
9.4 Serial data clock (CLK)
If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the
SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller.
On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from
the most to the less significant one (see Figure 5). When the SS
signal is high, slave not
selected, the microcontroller should drive the CLK low (the settings for the MCU SPI port
are CPHA = 0 and CPOL = 0).
9.5 Slave select (SS)
If SEL2 = H, the slave select (SS) signal is used to enable the VNI8200XP serial
communication shift register; data is flushed-in through the SDI pin and flushed-out from the
SDO pin only when the SS
pin is low. On the SS pin falling edge the shift register (containing
the fault conditions) is frozen, so any change on the power switches status is latched until
the next SS
falling edge event and the SDO output is enabled. On the SS pin rising edge
event the 8/16 bits present on the SPI shift register are evaluated and the outputs are driven
according to this frame. If more than 8/16 bits (depending on the SPI settings) are flushed
inside only the last 8/16 are evaluated; the others are flushed out from the SDO pin after
fault condition bits; in this way a proper communication is possible also in a daisy chain
configuration.
Figure 5. SPI mode diagram
9.6 8/16-bit selection (SEL1)
If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI
mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described
below.
CPHA=0
SCK
CPOL=0
SDO
SDI
Capture
Strobe
SS
Bit 1
Bit 1
Bit 2Bit 3
Bit 2
Bit 5
Bit 3
Bit 4
Bit 4
Bit 6
Bit 5
MSBit
Bit 6
LSBit
MSBit LSBit
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