Datasheet

DocID15234 Rev 6 19/40
VNI8200XP Functional pin description
9 Functional pin description
9.1 SPI/parallel selection mode (SEL2)
This pin allows the selection of the IC interfacing mode. The SPI interface is selected if
SEL2 = H, while the parallel interface is selected if SEL2 = L, according to Table 13:
9.2 Serial data in (SDI)
If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges
and, therefore, the microcontroller must change SDI state during the CLK falling edges.
After the SS
falling edge, the SDI is equal to the most significant bit of the control frame
(Figure 5).
9.3 Serial data out (SDO)
If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling
edges and, therefore, the microcontroller must read SDO state during the CLK rising edges.
The SDO pin is tri-stated when SS
signal is high and it is equal to the most significant bit of
the fault frame after the SS
falling edge (Figure 5).
Table 13. Pin description
Pin
Function
SEL2
(1)
= H
SPI operation
1. SEL2 has an internal weak pull-down.
SEL2 = L
Parallel operation
SDO/IN8 SDO Serial data output IN8 Input to channel 8
SS/IN7 SS Slave select IN7 Input to channel 7
CLK/IN6 CLK Serial clock IN6 Input to channel 6
SDI/IN5 SDI Serial data input IN5 Input to channel 5
WD/IN4 WD Watchdog input IN4 Input to channel 4
OUT_EN/IN3 OUT_EN
IC OUTPUT enable /
disable
IN3 Input to channel 3
WD_EN/IN2 WD_EN
Watchdog enable /
disable and timing
preset
IN2 Input to channel 2
SEL1/IN1 SEL1
8/16-bit SPI selection
mode
IN1 Input to channel 1