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This is information on a product in full production.

December 2013 DocID15234 Rev 6 1/40

VNI8200XP

Octal high-side smart power solid-state relay with serial/parallel

selectable interface on-chip

Datasheet

production data

Features

• Output current: 0.7 A per channel

• Serial/parallel selectable interface

• Short-circuit protection

• 8-bit and 16-bit SPI Interface for IC command

and control diagnostic

• Channel overtemperature detection and

protection

• Thermal independence of separate channels

• Drives all type of loads (resistive, capacitive,

inductive load)

• Loss of GND protection

• Power Good diagnostic

• Undervoltage shutdown with hysteresis

• Overvoltage protection (V

clamping)

• Very low supply current

• Common fault open drain output

• IC warning temperature detection

• Channel output enable

• 100 mA high efficiency step-down switching

regulator with integrated boot diode

• Adjustable regulator output

• Switching regulator disable

• 5 V and 3.3 V compatible I/Os

• Channel outputs status LED driving 4 x 2

multiplexed array

• Fast demagnetization of inductive loads

• ESD protection

• Designed to meet IEC 61131-2, IEC61000-4-4,

and IEC61000-4-5

Applications

• Programmable logic control

• Industrial PC peripheral input/output

• Numerical control machines

Type V

demag

(1)

1. Per channel

DS(on)

(1)

out

(1)

VNI8200XP V

-45 V 0.11 Ω 0.7 A 45 V

PowerSSO-36

Table 1. Device summary

Part number Package Packing

VNI8200XP

PowerSSO-36

Tube

VNI8200XPTR Tape and reel

www.st.com

Summary of content (40 pages)

PAGE 1
VNI8200XP Octal high-side smart power solid-state relay with serial/parallel selectable interface on-chip Datasheet - production data • Adjustable regulator output • Switching regulator disable • 5 V and 3.3 V compatible I/Os • Channel outputs status LED driving 4 x 2 multiplexed array • Fast demagnetization of inductive loads • ESD protection PowerSSO-36 • Designed to meet IEC 61131-2, IEC61000-4-4, and IEC61000-4-5 Features Type Vdemag(1) RDS(on)(1) VNI8200XP VCC-45 V Iout(1) VCC Applications 0.
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Contents VNI8200XP Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 5 Thermal data . . . . . .
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VNI8200XP 10 Contents 9.9 Fault indication (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.10 Power Good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.11 Programmable watchdog counter reset (WD) . . . . . . . . . . . . . . . . . . . . . 23 SPI operation (SEL2 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 10.1 8-bit SPI mode (SEL1 = L) . . . . . . . . . . . . . . . . . . . .
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List of tables VNI8200XP List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/40 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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VNI8200XP List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 VNI8200XP Description The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated SPI interface and high efficiency 100 mA micropower step-down switching regulator peak current control loop mode. The IC, realized in STMicroelectronics™ VIPower™ technology, is intended to drive any kind of load with one side connected to ground.
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VNI8200XP Block diagram '& '& &RQYHUWHU 8QGHUYROWDJH DQG 3RZHU *RRG 6(/ ,1 :'B(1 ,1 287B(1 ,1 :' ,1 6', ,1 9FF &ODPS &ODPS 3RZHU 63, /RJLF &/. ,1 66 ,1 6'2 ,1 &XUUHQW /LPLWHU -XQFWLRQ 7HP S 'HWHFWLRQ 6(/ 95(* 52: 52: 52: 9&& 3* '&9'' 95() 3+$6( )% %227 Figure 1.
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Pin connection 3 VNI8200XP Pin connection Figure 2. Pin connection (top view) 6(/ 1& 6(/ ,1 1& :'B(1 ,1 287 287B(1 ,1 287 :' ,1 287 6', ,1 287 &/. ,1 287 66 ,1 7$% 9FF 287 6'2 ,1 287 95(* 287 &2/ 1& &2/ %227 '& 9'' 3+$6( *1' 95() 52: )% 52: 7:$51 52: )$8/7 52: 3* $0 Y Table 2.
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VNI8200XP Pin connection Table 2. Pin description (continued) Pin Name Type Description 14 VREF Analog output Internally generated DC-DC voltage reference (To be connected to external 10 nF capacitor).
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Maximum ratings 4 VNI8200XP Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit 45 V -0.3 V VCC Power supply voltage -VCC Reverse supply voltage VREG Logic supply voltage -0.3 to +6 V Voltage range at pins TWARN, FAULT, PG -0.3 to +6 V VCC+6 V VFAULT VTWARN VPG VBOOT Bootstrap peak voltage VPHASE = Vcc VROW Voltage range at ROW pins -0.3 to +6 V VCOL Voltage range at COL pins -0.3 to +6 V Vdig Voltage level range at logic input pins -0.
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VNI8200XP 4.1 Electrical characteristics Thermal data Table 4. Thermal data Symbol Rth(JC) Rth(JA) Parameter Thermal resistance junction-case (1) Thermal resistance junction-ambient (2) Value Unit Max. 2 °C/W Max. 15 °C/W 1. Per channel. 2. PSSO36 mounted on the board STEVALIFP022V1 developed on four layer FR4, with about 8 cm2 for each layer. 5 Electrical characteristics 5.1 Power section 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 5.
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Electrical characteristics 5.2 VNI8200XP SPI characteristics 10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40
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VNI8200XP 5.4 Electrical characteristics Logic inputs 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 8. Logic inputs Symbol Parameter VIL Input low level voltage VIH Input high level voltage VI(HYST) IIN 5.5 Test conditions Min. Typ. Max. Unit 0.8 V 2.20 Input hysteresis voltage V 0.15 Input current VIN = 5 V V μΑ 8 Protection and diagnostic 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 9.
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Electrical characteristics VNI8200XP Table 9. Protection and diagnostic (continued) Symbol Hyst Parameter Test conditions ILIM tracking limits RLOAD = 0 ILFAULT FAULT leakage current ITWARN TWARN leakage current IPG PG leakage current TTSD Junction shutdown temperature Min. Typ. Max. 0.
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VNI8200XP Electrical characteristics Table 10. Step-down switching regulator (continued) Symbol Test conditions Ilim Limitation current Iqop Total operating quiescent current Iqst-by Min. Typ. Max. Unit 0.9 A 0.55 Total standby quiescent current Regulator standby 0.6 mA 15.8 µA fs Switching frequency 400 kHz Dmax Maximum duty cycle 80% % Minimum on-time 150 ns Frequency in short-circuit condition 50 kHz Tonmin fsc 5.7 Parameter LED driving array 10.
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Reverse polarity protection 6 VNI8200XP Reverse polarity protection Reverse polarity protection can be implemented on board using two different solutions: 1. Placing a resistor (RGND) between IC GND pin and load GND 2.
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VNI8200XP Demagnetization energy Figure 4. Maximum demagnetization energy vs. load current, typical values 5.10 Tamb= 125 °C 4.60 4.10 Single channel demagnetization 3.60 Four channels demagnetization 3.10 2.60 2.10 Eoff (J) 7 Demagnetization energy 1.60 1.10 0.60 0.10 0.1 0.3 0.5 0.7 0.9 Iout (A) DocID15234 Rev 6 1.
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Truth table 8 VNI8200XP Truth table Table 12.
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VNI8200XP Functional pin description 9 Functional pin description 9.1 SPI/parallel selection mode (SEL2) This pin allows the selection of the IC interfacing mode. The SPI interface is selected if SEL2 = H, while the parallel interface is selected if SEL2 = L, according to Table 13: Table 13.
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Functional pin description 9.4 VNI8200XP Serial data clock (CLK) If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller. On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from the most to the less significant one (see Figure 5).
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VNI8200XP 9.7 Functional pin description Output enable (OUT_EN) If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously. When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault conditions in the SPI register are latched. To enable the outputs it is then necessary to raise the OUT_EN pin and re-program the IC through the SPI interface.
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Functional pin description 9.9 VNI8200XP Fault indication (FAULT) The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or more of the following conditions: • Channel overtemperature (OVT) This pin is activated when at least one of the channels is in junction overtemperature.
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VNI8200XP 9.11 Functional pin description Programmable watchdog counter reset (WD) If SEL2 = H, the VNI8200XP embeds a watchdog counter that must be erased, with a negative pulse on the WD pin, before it expires. If the WD counter elapses, the VNI8200XP goes into an internal RESET state where all the outputs are disabled; to restart normal operation a negative pulse must be applied to the WD pin. The watchdog enable/disable pin should be connected through an external divider to VREG.
PAGE 24
SPI operation (SEL2 = H) VNI8200XP 10 SPI operation (SEL2 = H) 10.1 8-bit SPI mode (SEL1 = L) If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the microcontroller to the IC; each bit directly drives the corresponding output where LSB drives output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the corresponding output. At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller.
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VNI8200XP SPI operation (SEL2 = H) voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC warning case temperature, see Section 9.8), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the length is not a multiple of 8) and PG (Power Good, see Section 9.10).
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LED driving array 11 VNI8200XP LED driving array The LED driving array carries out the status of the output channels (ON or OFF) Figure 9. LED driving array 52: 52: 52: &2/ &2/ 95(* 67$786 67$786 67$786 67$786 67$786 67$786 67$786 52: 67$786 $0 Y The following is an indication of how to choose the Rext resistor value.
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VNI8200XP 12 Step-down switching regulator Step-down switching regulator The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current limit regulation is obtained in normal operation through a current loop control. A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage ripple; a low ESR (less than 10 mΩ) capacitor is preferable.
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/40 OPT_OUT_EN 3 3 C20 SDO 1 SS 1 CLK 1 SDI 1 OUT_EN DocID15234 Rev 6 R47 10k 115R 115R 100nF/10V GND LD9 1 LD10 1 LD11 1 Vreg PGOOD FAULT TWARN DC/DC OFF 3 LEDC-0603 1 CH2 LEDC-0603 LD4 2 1 CH4 LEDC-0603 CH6 2 LD6 1 LEDC-0603 CH8 2LD8 1 LEDC-0603 LD1 CH1 2 1 LEDC-0603 LD3 CH3 2 1 LEDC-0603 CH5 2 LD5 1 LEDC-0603 CH7 2 LD7 1 LD2 10nF/10V R52 10nF/10V R51 VNI8200 470R 2 TWARN LEDC-0603 2 FAULT LEDC-0603 R55 LEDC-0603 470R 470R 2 R53 R54 FB STPS1L60A 5V 2k37 1% low ESR< 10m
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287B(1 6'2 66 &/.
PAGE 30
Typical circuits and conventions VNI8200XP Figure 12. SPI directional logic convention 6', 9UHJ 66 &/.
PAGE 31
VNI8200XP 14 Thermal management Thermal management The power dissipation in the IC is the main factor that sets the safe operating condition of the device in the application. Therefore, it must be taken into account very carefully. Heatsinking can be achieved using copper on the PCB with proper area and thickness. The following image (Figure 13) shows the junction-to-ambient thermal impedance values for the PSSO36 package. Figure 13. PSSO36 thermal impedance vs.
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Thermal management 14.1 VNI8200XP Thermal behavior Figure 14. Thermal behavior 9LQ L + 287 L 2Q 67$7 L 2II + 1 12 7M L ! 7WVG <(6 287 L 2II 67$7 L 2Q / 4 <(6 7F ! 7FVG 12 2 <(6 12 7F ! 7FU 12 7M L ! 7MU <(6 3 $0 Y Note: 32/40 1 Thermal shutdown. 2 Junction hysteresis. 3 Restore to idle condition. 4 Case hysteresis.
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VNI8200XP 15 Interface timing diagram Interface timing diagram Figure 15. Serial timing Switching parameter test conditions Figure 16.
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Switching parameter test conditions VNI8200XP Figure 17.
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VNI8200XP 17 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 19. PowerSSO-36 mechanical data mm Symbol Min. Typ. Max. A 2.15 2.47 A2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 D 10.10 10.
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Package mechanical data VNI8200XP Figure 18. PowerSSO-36 package dimensions Figure 19. PowerSSO-36 tube shipment (no suffix) Table 20. PowerSSO-36 tube shipment Note: 36/40 Base quantity 49 Bulk quantity 1225 Tube length (± 0.5) 532 A 3.5 B 13.8 C (± 0.1) 0.6 All dimensions are in mm.
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VNI8200XP Package mechanical data Figure 20. PowerSSO-36 reel shipment (suffix “TR”) Table 21. PowerSSO-36 reel dimensions Base quantity 1000 Bulk quantity 1000 A (max.) 330 B (min.) 1.5 C (± 0.2) 13 F 20.2 G (2 ± 0) 24.4 N (min.) 100 T (max.) 30.
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Package mechanical data VNI8200XP Figure 21. PowerSSO-36 tape dimensions Table 22. PowerSSO-36 tape dimensions Note: 38/40 Tape width W 24 Tape hole spacing P0 (± 0.1) 4 Component spacing P 12 Hole diameter D (± 0.05) 1.55 Hole diameter D1 (min.) 1.5 Hole position F (± 0.1) 11.5 Compartment depth K (max.) 2.85 Hole spacing P1 (± 0.1) 2 According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb 1986.
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VNI8200XP 18 Revision history Revision history Table 23. Document revision history Date Revision 04-Dec-2008 1 Initial release 29-Apr-2009 2 Updated Table 5 on page 11 19-Jun-2012 3 Updated: Features,Section 9.4,Section 9.7,Section 9.9,Section 9.10, Section 12,Table 2,Table 3,Table 5,Table 7,Table 8,Table 9, Table 10,Table 11,Table 14,Figure 1,Figure 2. Changed: Figure 6,Figure 7,Figure 8,Figure 17,Figure 17. Content reworked to improve the readability.
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VNI8200XP Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.