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September 2013 Doc ID 7383 Rev 4 1/37

VNN7NV04, VNS7NV04

VND7NV04, VND7NV04-1

OMNIFET II

fully autoprotected Power MOSFET

Features

■

Linear current limitation

■

Thermal shutdown

■

Short circuit protection

■

Integrated clamp

■

Low current drawn from input pin

■

Diagnostic feedback through input pin

■

ESD protection

■

Direct access to the gate of the Power

MOSFET (analog driving)

■

Compatible with standard Power MOSFET in

compliance with the 2002/95/EC European

Directive

Description

The VNN7NV04, VNS7NV04, VND7NV04

VND7NV04-1, are monolithic devices designed in

STMicroelectronics VIPower M0-3 Technology,

intended for replacement of standard Power

MOSFETs from DC up to 50 kHz applications.

Built in thermal shutdown, linear current limitation

and overvoltage clamp protect the chip in harsh

environments.

Fault feedback can be detected by monitoring the

voltage at the input pin.

Type R

DS(on)

lim

clamp

VNN7NV04

VNS7NV04

VND7NV04

VND7NV04-1

60 mΩ 6A 40V

SOT-223

SO-8

TO251 (IPAK)

TO252 (DPAK)

Table 1. Device summary

Package

Order codes

Tube Tube (lead-free) Tape and reel Tape and reel (lead-free)

SOT-223 VNN7NV04 - VNN7NV0413TR -

SO-8 VNS7NV04 - VNS7NV0413TR -

TO-252 VND7NV04 VND7NV04-E VND7NV0413TR VND7NV04TR-E

TO-251 VND7NV04-1 VND7NV04-1-E - -

www.st.com

Summary of content (37 pages)

PAGE 1
VNN7NV04, VNS7NV04 VND7NV04, VND7NV04-1 OMNIFET II fully autoprotected Power MOSFET Features Type RDS(on) VNN7NV04 VNS7NV04 VND7NV04 VND7NV04-1 Ilim Vclamp 2 1 60 mΩ 6A 40 V 2 3 SO-8 SOT-223 ■ Linear current limitation ■ Thermal shutdown ■ Short circuit protection ■ Integrated clamp ■ Low current drawn from input pin ■ Diagnostic feedback through input pin ■ ESD protection ■ Direct access to the gate of the Power MOSFET (analog driving) ■ Compatible with standard Power MOSFET
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Contents VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 4 5 6 2/37 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. List of figures TO-252 (DPAK) package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 SOT-223 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 SO-8 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Block diagram and pin description 1 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Block diagram and pin description Figure 1. Block diagram DRAIN 2 Overvoltage Clamp INPUT 1 Gate Control Linear Current Limiter Over Temperature 3 SOURCE Figure 2. Configuration diagram (top view) SO-8 Package(1) SOURCE 1 8 DRAIN SOURCE INPUT DRAIN DRAIN SOURCE 4 5 DRAIN 1. For the pins configuration related to SOT-223, DPAK, IPAK see outlines at page 1.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 2 Electrical specifications Electrical specifications Figure 3. Current and voltage conventions ID VDS DRAIN IIN RIN INPUT SOURCE VIN 2.1 Absolute maximum ratings Table 2.
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Electrical specifications VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 2.2 Thermal data Table 3. Thermal data Value Symbol Parameter Unit SOT-223 Rthj-case Thermal resistance junction-case max Rthj-lead Thermal resistance junction-lead max Rthj-amb SO-8 DPAK IPAK 2.1 2.1 18 °C/W 27 Thermal resistance junction-ambient max (1) 96 (1) 90 °C/W 65 (1) 102 °C/W 1. When mounted on a standard single-sided FR4 board with 0.5 mm2 of Cu (at least 35 µm thick) connected to all DRAIN pins. 2.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Table 4. Symbol Electrical specifications Electrical characteristics (continued) Parameter Test conditions Min Typ Max Unit 100 300 ns 470 1500 ns 500 1500 ns 350 1000 ns 0.75 2.3 µs 4.6 14.0 µs 5.4 16.0 µs 3.6 11.0 µs Switching (Tj=25 °C, unless otherwise specified) td(on) tr td(off) tf td(on) tr td(off) tf (dI/dt)on Qi Turn-on delay time Rise time Turn-off delay time VDD=15 V; ID=3.
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Protection features 3 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features During normal operation, the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path. The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 kHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100µA) flows into the input pin in order to supply the internal circuitry.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Figure 4. Protection features Switching time test circuit for resistive load ID 90% tr tf 10% t td(on) Vgen td(off) t Figure 5. Test circuit for diode recovery times A A D I FAST DIODE OMNIFET S L=100uH B B 150Ω D Rgen VDD I Vgen OMNIFET S 8.
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Protection features Figure 6. VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Unclamped inductive load test circuits Figure 7. VIN RGEN VIN PW Figure 8.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features 3.1 Electrical characteristics curves Figure 9. Derating curve Figure 10. Transconductance Gfs (S) 20 18 Vds=13V 16 Tj=-40ºC Tj=25ºC 14 Tj=150ºC 12 10 8 6 4 2 0 0 1 2 3 4 5 6 7 8 Id(A) Figure 11. Static drain-source on resistance vs input voltage (part 1/2) Figure 12. Static drain-source on resistance vs input voltage (part 2/2) Rds(on) (mOhm) Rds(on) (mOhm) 140 120 110 120 Id=3.
PAGE 14
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Figure 15. Turn-on current slope (part 1/2) Figure 16. Turn-on current slope (part 2/2) di/dt(A/us) di/dt(A/us) 2.25 8 2 7 Vin=3.5V Vdd=15V Id=3.5A 1.75 Vin=5V Vdd=15V Id=3.5A 6 1.5 5 1.25 4 1 3 0.75 2 0.5 1 0.25 0 100 200 300 400 600 500 700 800 900 1000 1100 200 100 300 400 500 Rg(ohm) 600 700 800 900 1000 1100 Rg(ohm) Figure 17. Transfer characteristics Figure 18.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Protection features Figure 21. Turn-off drain source voltage slope Figure 22. Capacitance variations (part 2/2) C(pF) dv/dt(v/us) 600 300 250 500 f=1MHz Vin=0V Vin=3.5V Vdd=15V Id=3.5A 200 400 150 300 100 200 50 0 100 100 200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 30 35 Vds(V) Rg(ohm) Figure 23. Output characteristics Figure 24. Normalized on resistance vs temperature v ID(A) Rds(on) 12 2.
PAGE 16
Protection features VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Figure 27. Normalized input threshold voltage Figure 28. Normalized current limit vs junction vs temperature temperature Vin(th) Ilim (A) 1.15 15 14 1.1 Vds=Vin Id=1mA 1.05 Vds=13V Vin=5V 13 12 1 11 0.95 10 0.9 9 0.85 8 0.8 7 0.75 6 0.7 5 -50 -25 0 25 50 75 100 125 150 175 -50 T(ºC) Tdlim(us) 7 6.5 Vin=5V Rg=150ohm 5.5 5 4.5 4 3.5 5 10 15 20 25 30 35 Vdd(V) 16/37 0 25 50 75 Tj (ºC) Figure 29.
PAGE 17
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 3.2 Protection features SO-8 maximum demagnetization energy Figure 30. SO-8 maximum turn-off current versus load inductance ILMAX (A) 100 10 A B C 1 0.1 1 10 100 L(mH) Legend A = Single Pulse at TJstart=150 °C B = Repetitive pulse at TJstart=100 °C C = Repetitive Pulse at TJstart=125 °C Conditions: VCC=13.5 V Values are generated with RL=0 Ω.
PAGE 18
Protection features 3.3 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 DPAK maximum demagnetization energy Figure 32. DPAK maximum turn-off current versus load inductance ILM AX (A) 10 0 10 1 0.01 0.1 1 L (m H ) 10 100 Legend A = Single Pulse at TJstart=150 °C B = Repetitive pulse at TJstart=100 °C C = Repetitive Pulse at TJstart=125 °C Conditions: VCC=13.5 V Values are generated with RL=0 Ω.
PAGE 19
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 3.4 Protection features SOT-223 maximum demagnetization energy Figure 34. SOT-223 maximum turn-off current versus load inductance ILMAX (A) 100 10 1 0.01 0.1 1 10 L(mH) Legend A = Single Pulse at TJstart=150 °C B = Repetitive pulse at TJstart=100 °C C = Repetitive Pulse at TJstart=125 °C Conditions: VCC=13.5 V Values are generated with RL=0 Ω.
PAGE 20
Package and PCB thermal data VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 4 Package and PCB thermal data 4.1 SO-8 thermal data Figure 36. SO-8 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area=58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: 0.14 cm2, 0.8 cm2, 2 cm2). Figure 37. Rthj-amb vs PCB copper area in open box free air condition RTHj_amb (ºC/W) SO-8 at 2 pins connected to TAB 110 105 100 95 90 85 80 75 70 0 0.5 1 1.
PAGE 21
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data Figure 38. SO-8 thermal impedance junction ambient single pulse ZT H (°C /W) 1000 100 10 1 0.1 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000 Figure 39. Thermal fitting model of an OMNIFET II in SO-8 Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb Equation 1 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = t p ⁄ T Table 5.
PAGE 22
Package and PCB thermal data Table 5. 4.2 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 SO-8 thermal parameter (continued) Area/island (cm2) Footprint C2 (W.s/°C) 9.00E-04 C3 (W.s/°C) 7.50E-03 C4 (W.s/°C) 0.045 C5 (W.s/°C) 0.35 C6 (W.s/°C) 1.05 2 2 SOT-223 thermal data Figure 40. SOT-223 PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area=58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: 0.11 cm2, 1 cm2, 2 cm2). Figure 41.
PAGE 23
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data Figure 42. SOT-223 thermal impedance junction ambient single pulse ZT H (°C/W) 1000 100 10 1 0.1 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000 Figure 43. Thermal fitting model of an OMNIFET II in SOT-223 Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb Equation 2 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = t p ⁄ T Table 6.
PAGE 24
Package and PCB thermal data Table 6. 4.3 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 SOT-223 thermal parameter (continued) Area/island (cm2) Footprint C2 (W.s/°C) 9.00E-04 C3 (W.s/°C) 3.00E-02 C4 (W.s/°C) 0.16 C5 (W.s/°C) 1000 C6 (W.s/°C) 0.5 2 2 DPAK thermal data Figure 44. DPAK PC board Note: Layout condition of Rth and Zth measurements (PCB FR4 area=60 mm x 60 mm, PCB thickness=2 mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8 cm2). Figure 45.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Package and PCB thermal data Figure 46. DPAK thermal impedance junction ambient single pulse ZT H (°C/W) 1000 100 10 1 0.1 0.0001 0.001 0.01 0.1 1 T ime (s) 10 100 1000 Figure 47. Thermal fitting model of an OMNIFET II in DPAK Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb Equation 3 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = t p ⁄ T Table 7.
PAGE 26
Package and PCB thermal data Table 7. 26/37 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 DPAK thermal parameter (continued) Area/island (cm2) Footprint C1 (W.s/°C) 0.0006 C2 (W.s/°C) 0.0021 C3 (W.s/°C) 0.05 C4 (W.s/°C) 0.3 C5 (W.s/°C) 0.45 C6 (W.s/°C) 0.
PAGE 27
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 5 Package and packing information Package and packing information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.1 TO-251 (IPAK) mechanical data Table 8. TO-251 (IPAK) mechanical data millimeters Symbol Min. Typ. Max.
PAGE 28
Package and packing information VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Figure 48. TO-251 (IPAK) package dimensions 5.2 TO-252 (DPAK) mechanical data Table 9. TO-252 (DPAK) mechanical data millimeters Symbol Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.64 0.90 B2 5.20 5.40 C 0.45 0.60 C2 0.48 0.60 D 6.00 6.20 D1 E 28/37 Typ. 5.1 6.40 6.60 E1 4.7 e 2.28 G 4.40 4.60 H 9.35 10.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Table 9. Package and packing information TO-252 (DPAK) mechanical data (continued) millimeters Symbol Min. L2 Typ. Max. 0.8 L4 0.60 R 1.00 0.2 V2 0° Package Weight 8° Gr. 0.29 Figure 49. TO-252 (DPAK) package dimensions P032P 5.3 SOT-223 mechanical data Table 10. SOT-223 mechanical data millimeters Symbol Min. Typ. A Max. 1.8 B 0.6 0.7 0.85 B1 2.9 3 3.15 c 0.24 0.26 0.35 D 6.3 6.5 6.7 e 2.
PAGE 30
Package and packing information Table 10. VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 SOT-223 mechanical data (continued) millimeters Symbol Min. e1 Typ. Max. 4.6 E 3.3 3.5 3.7 H 6.7 7 7.3 V 10 (max) A1 0.02 0.1 Figure 50. SOT-223 package dimensions 0046067 5.4 SO-8 mechanical data Table 11. SO-8 mechanical data millimeters Symbol Min A a1 Max 1.75 0.1 a2 0.25 1.65 a3 0.65 0.85 b 0.35 0.48 A A1 30/37 Typ 1.75 0.10 Doc ID 7383 Rev 4 0.
PAGE 31
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Table 11. Package and packing information SO-8 mechanical data (continued) millimeters Symbol Min Typ Max A2 1.25 b 0.28 0.48 c 0.17 0.23 D(1) 4.80 4.90 5.00 E 5.80 6.00 6.20 E1(2) 3.80 3.90 4.00 e 1.27 h 0.25 0.50 L 0.40 1.27 L1 k 1.04 0° ccc 8° 0.10 1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm in total (both side). 2.
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Package and packing information 5.5 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 SOT-223 packing information Figure 52. SOT-223 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 12.4 60 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb.
PAGE 33
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 5.6 Package and packing information SO-8 packing information Figure 53. SO-8 tube shipment (no suffix) B C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) A 100 2000 532 3.2 6 0.6 Figure 54. SO-8 tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm.
PAGE 34
Package and packing information 5.7 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 DPAK packing information Figure 55. DPAK footprint and tube shipment (no suffix) A 6 .7 1 .8 3 .0 1 .6 C 2 .3 6 .7 2 .3 B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 75 3000 532 6 21.3 0.6 Figure 56. DPAK tape and reel shipment (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 16.4 60 22.
PAGE 35
VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 5.8 Package and packing information IPAK packing information Figure 57. IPAK tube shipment (no suffix) A C B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) 75 3000 532 6 21.3 0.6 All dimensions are in mm.
PAGE 36
Revision history 6 VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Revision history Table 12. 36/37 Document revision history Date Revision Changes 01-Feb-2003 1 Initial Release 28-Apr-2009 2 Added Table 1: Device summary on page 1 and Section 4: Package and PCB thermal data on page 20. Updated Section 5: Package and packing information on page 27. 10-Sep-2010 3 Updated Table 4: Electrical characteristics 20-Sep-2013 4 Updated Disclaimer.
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VNN7NV04, VNS7NV04, VND7NV04, VND7NV04-1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.