Datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- Table 5. Power section
- Table 6. Switching (VCC = 24 V; Tj = 25 C)
- Table 7. Logic inputs
- Figure 4. Treset definition
- Figure 5. Tstby definition
- Table 8. Protections and diagnostics
- Table 9. Current sense (8 V < VCC < 36 V)
- Table 10. Openload detection (VFR_Stby = 5 V)
- Figure 6. Current sense delay characteristics
- Figure 7. Openload off-state delay timing
- Figure 8. Switching characteristics
- Figure 9. Output stuck to VCC detection delay time at FRSTBY activation
- Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense
- Figure 11. Output voltage drop limitation
- Figure 12. Device behavior in overload condition
- Table 11. Truth table
- Table 12. Electrical transient requirements (part 1)
- Table 13. Electrical transient requirements (part 2)
- Table 14. Electrical transient requirements (part 3)
- 2.4 Electrical characteristics curves
- Figure 13. Off-state output current
- Figure 14. High-level input current
- Figure 15. Input clamp voltage
- Figure 16. High-level input voltage
- Figure 17. Low-level input voltage
- Figure 18. Input hysteresis voltage
- Figure 19. On-state resistance vs Tcase
- Figure 20. On-state resistance vs VCC
- Figure 21. ILIMH vs Tcase
- Figure 22. Turn-on voltage slope
- Figure 23. Turn-off voltage slope
- 3 Application information
- 4 Package and PCB thermal data
- 4.1 PowerSSO-24 thermal data
- Figure 26. PowerSSO-24 PC board
- Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)
- Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
- Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
- Table 15. Thermal parameters
- 4.1 PowerSSO-24 thermal data
- 5 Package and packing information
- 6 Order codes
- 7 Revision history

VND5T035AK-E Application information
Doc ID 018942 Rev 5 21/31
3.1.2 Solution 2: diode (D
GND
) in the ground line
A resistor (R
GND
=4.7kΩ) should be inserted in parallel to D
GND
if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network produces a shift (≈600 mV) in the input threshold
and in the status output values, if the microprocessor ground is not common to the device
ground. This shift does not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
D
ld
is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to
V
CC
maximum DC rating. The same applies if the device is subject to transients on the V
CC
line that are greater than the ones shown in the ISO T/R 7637/2 table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient is present on the V
CC
line, the
control pins are pulled negative. ST suggests that a resistor (R
prot
) have to be inserted in
line to prevent the microcontroller I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of the
microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the
latch-up limit of microcontroller I/Os.
-V
CCpeak
/I
latchup
≤ R
prot
≤ (V
OHμC
-V
IH
-V
GND
) / I
IHmax
Calculation example:
For V
CCpeak
= -600 V and I
latchup
≥ 20 mA; V
OHμC
≥ 4.5 V
30 kΩ ≤ R
prot
≤ 180 kΩ.
Recommended R
prot
value is 60 kΩ.