Datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- Table 5. Power section
- Table 6. Switching (VCC = 24 V; Tj = 25 C)
- Table 7. Logic inputs
- Figure 4. Treset definition
- Figure 5. Tstby definition
- Table 8. Protections and diagnostics
- Table 9. Current sense (8 V < VCC < 36 V)
- Table 10. Openload detection (VFR_Stby = 5 V)
- Figure 6. Current sense delay characteristics
- Figure 7. Openload off-state delay timing
- Figure 8. Switching characteristics
- Figure 9. Output stuck to VCC detection delay time at FRSTBY activation
- Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense
- Figure 11. Output voltage drop limitation
- Figure 12. Device behavior in overload condition
- Table 11. Truth table
- Table 12. Electrical transient requirements (part 1)
- Table 13. Electrical transient requirements (part 2)
- Table 14. Electrical transient requirements (part 3)
- 2.4 Electrical characteristics curves
- Figure 13. Off-state output current
- Figure 14. High-level input current
- Figure 15. Input clamp voltage
- Figure 16. High-level input voltage
- Figure 17. Low-level input voltage
- Figure 18. Input hysteresis voltage
- Figure 19. On-state resistance vs Tcase
- Figure 20. On-state resistance vs VCC
- Figure 21. ILIMH vs Tcase
- Figure 22. Turn-on voltage slope
- Figure 23. Turn-off voltage slope
- 3 Application information
- 4 Package and PCB thermal data
- 4.1 PowerSSO-24 thermal data
- Figure 26. PowerSSO-24 PC board
- Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)
- Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
- Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
- Table 15. Thermal parameters
- 4.1 PowerSSO-24 thermal data
- 5 Package and packing information
- 6 Order codes
- 7 Revision history

VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 17/31
Table 12. Electrical transient requirements (part 1)
ISO 7637-2:
2004(E)
Test pulse
Test levels
(1)
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III IV
1 - 450 V - 600 V
5000
pulses
0.5 s 5 s 1 ms, 50 Ω
2a + 37 V + 50 V
5000
pulses
0.2 s 5 s 50 µs, 2 Ω
3a - 150 V - 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b + 150 V + 200 V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 - 12 V - 16 V 1 pulse 100 ms, 0.01
Ω
5b
(1)
1. Valid in case of external load dump clamp: 58 V maximum referred to ground.
+ 123 V + 174 V 1 pulse 350 ms, 1
Ω
Table 13. Electrical transient requirements (part 2)
(1)
1. In order to guarantee the ISO transient classes a minimum 10KΩ protection resistors are needed on logic
pins
ISO 7637-2:
2004(E)
Test pulse
Test level results
III IV
1C C
2a C C
3a C C
3b
(2)
2. Without capacitor between V
CC
and GND.
EE
3b
(3)
3. With 10 nF between V
CC
and GND.
CC
4C C
5b
(4)
4. External load dump clamp, 58 V maximum, referred to ground.
CC
Table 14. Electrical transient requirements (part 3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.