Datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- Table 5. Power section
- Table 6. Switching (VCC = 24 V; Tj = 25 C)
- Table 7. Logic inputs
- Figure 4. Treset definition
- Figure 5. Tstby definition
- Table 8. Protections and diagnostics
- Table 9. Current sense (8 V < VCC < 36 V)
- Table 10. Openload detection (VFR_Stby = 5 V)
- Figure 6. Current sense delay characteristics
- Figure 7. Openload off-state delay timing
- Figure 8. Switching characteristics
- Figure 9. Output stuck to VCC detection delay time at FRSTBY activation
- Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense
- Figure 11. Output voltage drop limitation
- Figure 12. Device behavior in overload condition
- Table 11. Truth table
- Table 12. Electrical transient requirements (part 1)
- Table 13. Electrical transient requirements (part 2)
- Table 14. Electrical transient requirements (part 3)
- 2.4 Electrical characteristics curves
- Figure 13. Off-state output current
- Figure 14. High-level input current
- Figure 15. Input clamp voltage
- Figure 16. High-level input voltage
- Figure 17. Low-level input voltage
- Figure 18. Input hysteresis voltage
- Figure 19. On-state resistance vs Tcase
- Figure 20. On-state resistance vs VCC
- Figure 21. ILIMH vs Tcase
- Figure 22. Turn-on voltage slope
- Figure 23. Turn-off voltage slope
- 3 Application information
- 4 Package and PCB thermal data
- 4.1 PowerSSO-24 thermal data
- Figure 26. PowerSSO-24 PC board
- Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)
- Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
- Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
- Table 15. Thermal parameters
- 4.1 PowerSSO-24 thermal data
- 5 Package and packing information
- 6 Order codes
- 7 Revision history

VND5T035AK-E Electrical specifications
Doc ID 018942 Rev 5 13/31
Figure 6. Current sense delay characteristics
Figure 7. Openload off-state delay timing
Note: Vfr_stby = high
Table 10.
Openload detection (V
FR_Stby
=5V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
OL
Openload off-state
voltage detection
threshold
V
IN
=0V; 8V<V
CC
<36V 2 4 V
t
DSTKON
Output short circuit to
V
CC
detection delay at
turn off
See Figure 7 180 1800 µs
I
L(off2)
Off-state output current
at V
OUT
= 4V
V
IN
=0V; V
SENSE
=0V;
V
OUT
rising from 0 V to 4 V
-120 0 µA
td_vol
Delay response from
output rising edge to
V
SENSE
rising edge in
openload
V
OUT
=4V; V
IN
=0V;
V
SENSE
= 90 % of V
SENSEH
;
R
SENSE
=3.9K
20 µs
t
DFRSTK_ON
Output short circuit to
V
CC
detection delay at
FRSTBY activation
See Figure 9; Input
1,2
= low 50 µs
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