Datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- Table 5. Power section
- Table 6. Switching (VCC = 24 V; Tj = 25 C)
- Table 7. Logic inputs
- Figure 4. Treset definition
- Figure 5. Tstby definition
- Table 8. Protections and diagnostics
- Table 9. Current sense (8 V < VCC < 36 V)
- Table 10. Openload detection (VFR_Stby = 5 V)
- Figure 6. Current sense delay characteristics
- Figure 7. Openload off-state delay timing
- Figure 8. Switching characteristics
- Figure 9. Output stuck to VCC detection delay time at FRSTBY activation
- Figure 10. Delay response time between rising edge of ouput current and rising edge of current sense
- Figure 11. Output voltage drop limitation
- Figure 12. Device behavior in overload condition
- Table 11. Truth table
- Table 12. Electrical transient requirements (part 1)
- Table 13. Electrical transient requirements (part 2)
- Table 14. Electrical transient requirements (part 3)
- 2.4 Electrical characteristics curves
- Figure 13. Off-state output current
- Figure 14. High-level input current
- Figure 15. Input clamp voltage
- Figure 16. High-level input voltage
- Figure 17. Low-level input voltage
- Figure 18. Input hysteresis voltage
- Figure 19. On-state resistance vs Tcase
- Figure 20. On-state resistance vs VCC
- Figure 21. ILIMH vs Tcase
- Figure 22. Turn-on voltage slope
- Figure 23. Turn-off voltage slope
- 3 Application information
- 4 Package and PCB thermal data
- 4.1 PowerSSO-24 thermal data
- Figure 26. PowerSSO-24 PC board
- Figure 27. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)
- Figure 28. PowerSSO-24 thermal impedance junction ambient single pulse (one channel ON)
- Figure 29. Thermal fitting model of a double channel HSD in PowerSSO-24
- Table 15. Thermal parameters
- 4.1 PowerSSO-24 thermal data
- 5 Package and packing information
- 6 Order codes
- 7 Revision history

Electrical specifications VND5T035AK-E
12/31 Doc ID 018942 Rev 5
Table 9. Current sense (8 V < V
CC
<36V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
K
1
I
OUT
/I
SENSE
I
OUT
= 1 A; V
SENSE
= 2 V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C
1952
2080
2960
4150
3840
dK
1
/K
1
(1)
1. Parameter guaranteed by design; it is not tested.
Current sense ratio drift
I
OUT
= 1 A; V
SENSE
= 2 V;
T
j
= -40°C to 150°C
-15 15 %
K
2
I
OUT
/I
SENSE
I
OUT
= 3 A; V
SENSE
= 4 V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C
2490
2585
2930
3440
3265
dK
2
/K
2
(1)
Current sense ratio drift
I
OUT
= 3 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C
-10 +10 %
K
3
I
OUT
/I
SENSE
I
OUT
= 12 A; V
SENSE
= 4 V;
T
j
= -40°C...150°C
T
j
= 25°C...150°C
2770
2755
2900
3125
3045
dK
3
/K
3
(1)
Current sense ratio drift
I
OUT
= 12 A; V
SENSE
= 4 V;
T
j
= -40°C to 150°C
-5 5 %
I
SENSE0
Analog sense leakage
current
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 0 V; T
j
= -40°C...150°C
01µA
I
OUT
= 0 A; V
SENSE
= 0 V;
V
IN
= 5 V; T
j
= -40°C...150°C
02µA
V
SENSE
Max analog sense output
voltage
I
OUT
= 12 A; R
SENSE
=3.9KΩ 5V
V
SENSEH
Analog sense output
voltage in fault
condition
(2)
2. Fault condition includes: power limitation, overtemperature and open load in off-state condition.
V
CC
=24V; R
SENSE
= 3.9 KΩ 7.5 8.5 9.5 V
I
SENSEH
Analog sense output
current in fault condition
(2)
V
CC
= 24 V; V
SENSE
= 5 V 4.9 9 12 mA
t
DSENSE2H
Delay response time
from rising edge of
INPUT pins
V
SENSE
<4V;
0.2 A < I
OUT
<12A;
I
SENSE
=90% of I
SENSE
max
;
(see Figure 6)
200 400 µs
Δt
DSEN
SE
2H
Delay response time
between rising edge of
output current and rising
edge of current sense
V
SENSE
<4V;
I
SENSE
= 90 % of I
SENSEMAX
;
I
OUT
=90% of I
OUTMAX
;
I
OUTMAX
= 3 A (see Figure 10)
250 µs
t
DSENSE2L
Delay response time
from falling edge of
INPUT pins
V
SENSE
<4V;
0.2 A < I
OUT
<12A;
I
SENSE
=10% of I
SENSE
max
;
(see Figure 6)
520µs