Datasheet

VND5E160J-E Electrical specifications
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Figure 6. Switching characteristics
Table 11. Truth table
Conditions INPUTn OUTPUTn STATUSn (V
SD
=0V)
(1)
1. If the V
SD
is high, the STATUS pin is in a high impedance.
Normal operation
L
H
L
H
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overload &
Short circuit to GND
H
H
X
(no power limitation)
Cycling
(power limitation)
H
L
Output voltage > V
OL
L
H
H
H
L
(2)
H
2. The STATUS pin is low with a delay equal to t
DSTKON
after INPUT falling edge.
Output current < I
OL
L
H
L
H
H
(3)
L
3. The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10%
t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%
t
Won
t
Woff