Datasheet

VND5E160J-E Electrical specifications
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Table 9. Open load detection (8V<V
CC
<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
OL
Openload ON state
detection threshold
V
IN
= 5V 10 40 mA
t
DOL(on)
Openload ON state
detection delay
I
OUT
= 0A, V
CC
=13V
(See Figure 4.)
200 µs
t
POL
Delay between INPUT
falling edge and
STATUS rising edge in
open load condition
I
OUT
= 0A (see Figure 4.) 200 500 1200 µs
V
OL
Openload OFF state
voltage detection
threshold
V
IN
= 0V 2 4 V
t
DSTKON
Output short circuit to
V
cc
detection delay at
turn off
(See Figure 4.)180t
POL
µs
I
L(off2)
Off state output
current
(1)
1. For each channel.
V
IN
= 0V; V
OUT
= 4V
(see Section 3.4: Open load
detection in Off state)
-75 0 µA
td_vol
Delay response from
output rising edge to
STATUS falling edge in
open load
V
IN
= 0V; V
OUT
= 4V 20 µs
Table 10. Logic Input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level 0.9 V
I
IL
Low level input current V
IN
= 0.9V 1 µA
V
IH
Input high level 2.1 V
I
IH
High level input current V
IN
= 2.1V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level voltage 0.9 V
I
SDL
Low level STAT_DIS current V
SD
=0.9V 1 µA
V
SDH
STAT_DIS high level voltage 2.1 V
I
SDH
High level STAT_DIS current V
SD
=2.1V 10 µA
V
SD(hyst)
STAT_DIS hysteresis voltage 0.25 V
V
SDCL
STAT_DIS clamp voltage
I
SD
=1mA
I
SD
=-1mA
5.5
-0.7
7V
V