Datasheet

VND5E050K-E Electrical specifications
Doc ID 14472 Rev 4 13/40
Figure 6. Switching characteristics
Table 11. Truth table
Conditions Input Output Sense (V
CSD
=0V)
(1)
1. If the V
CSD
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Normal operation
L
H
L
H
H
H
Over temperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Overload and
short circuit to GND
H
H
X
(no power limitation)
Cycling
(power limitation)
H
L
Output voltage > V
OL
L
H
H
H
L
(2)
H
2. The STATUS pin is low with a delay equal to t
DSTKON
after INPUT falling edge.
Output current < I
OL
L
H
L
H
H
(3)
L
3. The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
V
OUT
dV
OUT
/dt
(on)
t
r
80%
10%
t
f
dV
OUT
/dt
(off)
t
d(off)
t
d(on)
INPUT
t
t
90%