Datasheet

VND5E050K-E Electrical specifications
Doc ID 14472 Rev 4 11/40
t
POL
Delay between input
falling edge and status
rising edge in open-load
condition
I
OUT
= 0A (see Figure 4) 200 500 1200 µs
V
OL
Openload off-state
voltage detection
threshold
V
IN
= 0V; 2 4 V
t
DSTKON
Output short circuit to
V
CC
detection delay at
turn-off
See Figure 4 180 t
POL
µs
I
L(off2)
Off-state output
current
(1)
V
IN
= 0V; V
OUT
= 4V
(see Section 3.4: Open-load
detection in off-state)
-75 0 µA
td_vol
Delay response from
output rising edge to
status falling edge in
open-load
V
IN
= 0V; V
OUT
= 4V 20 µs
1. For each channel.
Table 10. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
IL
Input low level 0.9 V
I
IL
Low level input current V
IN
=0.9 V 1 µA
V
IH
Input high level 2.1 V
I
IH
High level input current V
IN
= 2.1 V 10 µA
V
I(hyst)
Input hysteresis voltage 0.25 V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
STAT_DIS low level voltage 0.9 V
I
SDL
Low level STAT_DIS current V
SD
= 0.9 V 1 µA
V
SDH
STAT_DIS high level voltage 2.1 V
I
SDH
High level STAT_DIS current V
SD
= 2.1 V 10 µA
V
SD(hyst)
STAT_DIS hysteresis voltage 0.25 V
V
SDCL
STAT_DIS clamp voltage
I
SD
=1mA
I
SD
=-1mA
5.5
-0.7
7V
V
Table 9. Openload detection (8V<V
CC
<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit