Datasheet

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VND5E006ASP-E Electrical specifications
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Table 12. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
Test Pulse
Test levels
(1)
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
impedance
III IV
1 -75 V -100 V
5000
pulses
0.5 s 5 s 2 ms, 10 Ω
2a +37 V +50 V
5000
pulses
0.2 s 5 s 50 μs, 2 Ω
3a -100 V -150 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
3b +75 V +100 V 1h 90 ms 100 ms 0.1 μs, 50 Ω
4 -6 V -7 V 1 pulse 100 ms, 0.01
Ω
5b
(2)
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
+65 V +87 V 1 pulse 400 ms, 2 Ω
Table 13. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E)
Test Pulse
Test level results
(1)
1. The above test levels must be considered referred to V
CC
= 13.5 V except for pulse 5b.
III IV
1C C
2a C C
3a C C
3b C C
4C C
5b
(2)(3)
2. Valid in case of external load dump clamp: 40V maximum referred to ground. The protection strategy
allows PowerMOS to be cyclically switched on during load dump, so distributing the load dump energy
along the time and to transfer a part of it to the load.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum ratings.
CC
Table 14. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure
to disturbance and cannot be returned to proper operation without replacing the