Datasheet

VND5050J-E / VND5050K-E Electrical specifications
Doc ID 12266 Rev 7 9/37
I
L(off1)
Off-state output
current
(2)
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=25°C
V
IN
=V
OUT
=0V; V
CC
=13V;
T
j
=125°C
0
0
0.01 3
5
µA
I
L(off2)
Off-state output
current
(2)
V
IN
=0V; V
OUT
=4V -75 0
V
F
Output - V
CC
diode
voltage
(2)
-I
OUT
=4A; T
j
=150°C 0.7 V
1. PowerMOS leakage included.
2. For each channel.
Table 7. Switching (V
CC
= 13V; T
j
= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
Turn-on delay time R
L
= 6.5 Ω (see Figure 5 )20µs
t
d(off)
Turn-off delay time R
L
= 6.5 Ω (see Figure 5 )40µs
dV
OUT
/dt
(on)
Turn-on voltage slope R
L
= 6.5 Ω See Figure 22 V / µs
dV
OUT
/dt
(off)
Turn-off voltage slope R
L
= 6.5 Ω See Figure 24 V / µs
W
ON
Switching energy losses
during t
won
R
L
= 6.5 Ω (see Figure 5 )0.21mJ
W
OFF
Switching energy losses
during t
woff
R
L
= 6.5 Ω (see Figure 5 )0.28mJ
Table 8. Status pin (V
SD
=0V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
STAT
Status low output
voltage
I
STAT
= 1.6 mA, V
SD
=0V 0.5 V
I
LSTAT
Status leakage current
Normal operation or V
SD
=5V,
V
STAT
= 5V
10 µA
C
STAT
Status pin input
capacitance
Normal operation or V
SD
=5V,
V
STAT
= 5V
100 pF
V
SCL
Status clamp voltage
I
STAT
= 1mA
I
STAT
= -1mA
5.5
-0.7
7V
V
Table 6. Power section (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit