Datasheet

VND5050AJ-E / VND5050AK-E Electrical specifications
Doc ID 12272 Rev 10 11/37
dK
2
/K
2
(1)
Current sense ratio
drift
I
OUT
=2 A; V
SENSE
= 4 V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
-4 +4 %
K
3
I
OUT
/I
SENSE
I
OUT
=4A; V
SENSE
=4V;V
CSD
=0V;
T
j
=-40°C
T
j
=25°C...150°C
1880
1900
2010
2010
2160
2120
dK
3
/K
3
(1)
Current sense ratio
drift
I
OUT
=4 A; V
SENSE
= 4 V;
V
CSD
=0V;
T
J
=-40 °C to 150 °C
-2 +2 %
I
SENSE0
Analog sense
leakage current
I
OUT
=0A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=0V;
T
j
=-40°C...150°C
V
CSD
=0V; V
IN
=5V;
T
j
=-40°C...150°C
I
OUT
=2A; V
SENSE
=0V;
V
CSD
=5V; V
IN
=5V;
T
j
=-40°C...150°C
0
0
0
1
2
1
µA
µA
µA
I
OL
Openload on-state
current detection
threshold
V
IN
= 5V, I
SENSE
= 5 µA 4 20 mA
V
SENSE
Max analog sense
output voltage
I
OUT
=4A; V
CSD
=0V 5 V
V
SENSEH
Analog sense
output voltage in
over temperature
condition
V
CC
=13V; R
SENSE
=10KΩ 9V
I
SENSEH
Analog sense
output current in
over temperature
condition
V
CC
=13V; V
SENSE
=5V 8 mA
t
DSENSE1H
Delay response
time from falling
edge of CS_DIS
pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=90% of I
SENSE max
(see Figure 4)
50 100 µs
t
DSENSE1L
Delay response
time from rising
edge of CS_DIS
pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=10% of I
SENSE max
(see Figure 4)
520µs
t
DSENSE2H
Delay response
time from rising
edge of INPUT pin
V
SENSE
<4V, 0.5A<Iout<4A
I
SENSE
=90% of I
SENSE max
(see Figure 4)
80 250 µs
Table 10. Current sense (8V<V
CC
<16V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit