Datasheet

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September 2013 Doc ID 7393 Rev 9 1/31

VNB14NV04, VND14NV04

VND14NV04-1, VNS14NV04

"OMNIFET II"

fully autoprotected Power MOSFET

Features

■

Linear current limitation

■

Thermal shutdown

■

Short circuit protection

■

Integrated clamp

■

Low current drawn from input pin

■

Diagnostic feedback through input pin

■

ESD protection

■

Direct access to the gate of the Power

MOSFET (analog driving)

■

Compatible with standard Power MOSFET

Description

The

VNB14NV04, VND14NV04, VND14NV04-1 and

VNS14NV04

are monolithic devices made using

STMicroelectronics VIPower™ M0 technology,

intended for replacement of standard power

MOSFETS in DC to 50 KHz applications. Built-in

thermal shutdown, linear current limitation and

overvoltage clamp protect the chip in harsh

environments.

Fault feedback can be detected by monitoring the

voltage at the input pin.

TYPE R

DS(on)

lim

clamp

VNB14NV04

VND14NV04

VND14NV04-1

VNS14NV04

35 mΩ 12 A 40 V

TO-252 (DPAK)

TO-251 (IPAK)

SO-8 D

PAK

Table 1. Device summary

Package Tube Tube (lead free) Tape and reel Tape and reel (lead free)

PAK VNB14NV04 VNB14NV04-E

VNB14NV0413TR VNB14NV04TR-E

TO-252 (DPAK) VND14NV04 VND14NV04-E

VND14NV0413TR VND14NV04TR-E

TO-251 (IPAK) VND14NV04-1 VND14NV04-1-E -

SO-8 VNS14NV04 - -

www.st.com

Summary of content (31 pages)

PAGE 1
VNB14NV04, VND14NV04 VND14NV04-1, VNS14NV04 "OMNIFET II" fully autoprotected Power MOSFET Features TYPE RDS(on) VNB14NV04 VND14NV04 VND14NV04-1 VNS14NV04 Ilim 3 Vclamp TO-252 (DPAK) 35 mΩ 12 A 3 2 1 1 TO-251 (IPAK) 40 V 3 1 ■ Linear current limitation ■ Thermal shutdown ■ Short circuit protection ■ Integrated clamp ■ Low current drawn from input pin ■ Diagnostic feedback through input pin ■ ESD protection ■ Direct access to the gate of the Power MOSFET (analog driving) ■ Compa
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Contents VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of figures VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 1 Block diagram Block diagram Figure 1.
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Electrical specification 2 VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Electrical specification Figure 2. Current and voltage conventions 2.1 Absolute maximum rating Table 2.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 2.2 Thermal data Table 3. Thermal data Electrical specification Value Symbol Parameter SO-8 Rthj-case Thermal resistance junction-case max Rthj-lead Thermal resistance junction-lead max Rthj-amb DPAK IPAK D2PAK 1.7 1.7 1.7 °C/W 27 (1) Thermal resistance junction-ambient max 90 Unit °C/W (1) 65 102 52 (1) °C/W 1. When mounted on a standard single-sided FR4 board with 0.5 cm2 of Cu (at least 35 µm thick) connected to all DRAIN pins.
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Electrical specification Table 4. Electrical characteristics (continued) Symbol td(on) tr td(off) tf (di/dt)on VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Parameter Test Conditions Min Turn-on delay time Rise time Turn-off delay time VDD = 15 V Id = 7 A Vgen = 5 V Rgen = 2.2 KΩ (see Figure 3) Fall time Typ Max Unit 1.5 4.5 µs 9.7 30.0 µs 25.0 µs 30.0 µs 10.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 3 Protection features Protection features During normal operation, the input pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 50 KHz. The only difference from the user’s standpoint is that a small DC current IISS (typ. 100 µA) flows into the input pin in order to supply the internal circuitry.
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Protection features 10/31 VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Figure 3. Switching time test circuit for resistive load Figure 4.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Figure 5. Unclamped inductive load test circuits Figure 7. Input charge test circuit Figure 6.
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Protection features Figure 8. VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Source-drain diode forward characteristics Figure 9. Static drain source on resistance Figure 10. Derating curve Figure 11. Static drain-source on resistance vs. input voltage (part 1/2) Figure 12. Static drain-source on resistance vs. input voltage (part 2/2) Figure 13.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Protection features Figure 14. Static drain-source on resistance vs. id Figure 15. Transfer characteristics Figure 16. Turn-on current slope (part 1/2) Figure 17. Turn-on current slope (part 2/2) Figure 18. Input voltage vs. input charge Figure 19.
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Protection features VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Figure 20. Turn-off drain source voltage slope Figure 21. Capacitance variations (part 2/2) Figure 22. Switching time resistive load (part 1/2) Figure 23. Switching time resistive load (part 2/2) Figure 24. Output characteristics Figure 25. Normalized on resistance vs.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Protection features Figure 26. Normalized input threshold voltage Figure 27. Current limit vs. junction vs. temperature temperatures Figure 28.
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Protection features VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Figure 29. DPAK maximum turn-off current versus load inductance Legend: A= Single pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive pulse at TJstart=125ºC Conditions: VCC=13.5 V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. Figure 30.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Protection features Figure 31. D2PAK maximum turn-off current versus load inductance Legend: A= Single pulse at TJstart=150ºC B= Repetitive pulse at TJstart=100ºC C= Repetitive pulse at TJstart=125ºC Conditions: VCC=13.5 V Values are generated with RL=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. Figure 32.
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Package thermal data VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 4 Package thermal data 4.1 DPAK thermal data Figure 33. DPAK PC board(1) 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 60 mm x 60 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: from minimum pad lay-out to 8 cm2). Figure 34.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Package thermal data Figure 35. DPAK thermal impedance junction ambient single pulse Figure 36. Thermal fitting model of an OMNIFET II in DPAK Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = t p ⁄ T Table 5. DPAK thermal parameter Area/island(cm2) Footprint R1 (°C/W) 0.1 R2 (°C/W) 0.35 R3 ( °C/W) 1.20 R4 (°C/W) 2 R5 (°C/W) 15 R6 (°C/W) 61 C1 (W.s/°C) 0.0006 C2 (W.s/°C) 0.0021 C3 (W.s/°C) 0.
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Package thermal data Table 5. 4.2 VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 DPAK thermal parameter (continued) Area/island(cm2) Footprint C4 (W.s/°C) 0.3 C5 (W.s/°C) 0.45 C6 (W.s/°C) 0.8 6 5 SO-8 thermal data Figure 37. SO-8 PC board(1) 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 58 mm x 58 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: 0.14 cm2, 0.6 cm2, 1.6 cm2). Figure 38.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 4.3 Package thermal data D2PAK thermal data Figure 39. D2PAK PC board(1) 1. Layout condition of Rth and Zth measurements (PCB FR4 area = 60 mm x 60 mm, PCB thickness=2 mm, Cu thickness=35 µm, Copper areas: from minimum pad lay-out to 8 cm2). Figure 40.
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Package thermal data VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Figure 41. D2PAK thermal impedance junction ambient single pulse Figure 42. Thermal fitting model of an OMNIFET II in D2PAK Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = t p ⁄ T Table 6. 22/31 D2PAK thermal parameter Area/island(cm2) Footprint R1 (°C/W) 0.1 R2 (°C/W) 0.35 R3 ( °C/W) 0.3 R4 (°C/W) 4 R5 (°C/W) 9 R6 (°C/W) 37 C1 (W.s/°C) 0.0006 C2 (W.s/°C) 2.
PAGE 23
VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Table 6. Package thermal data D2PAK thermal parameter (continued) Area/island(cm2) Footprint C3 (W.s/°C) 8.00E-02 C4 (W.s/°C) 0.45 C5 (W.s/°C) 2 C6 (W.
PAGE 24
Package information VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 5 Package information 5.1 ECOPACK® In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 5.2 TO-251 (IPAK) mechanical data Figure 43. TO-251 (IPAK) package dimension Table 7.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Table 7. Package information TO-251 (IPAK) mechanical data (continued) Millimeters Dim. Min. Typ. B3 0.85 B5 0.3 B6 0.95 C 0.45 0.6 C2 0.48 0.6 D 6 6.2 E 6.4 6.6 G 4.4 4.6 H 15.9 16.3 L 9 9.4 L1 0.8 1.2 L2 5.3 Max. 0.8 1 D2PAK mechanical data Figure 44.
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Package information VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 D2PAK mechanical data Table 8. Millimeters Dim. Min. Max. A 4.4 4.6 A1 2.49 2.69 A2 0.03 0.23 B 0.7 0.93 B2 1.14 1.7 C 0.45 0.6 C2 1.23 1.36 D 8.95 9.35 D1 E 8 10 E1 10.4 8.5 G 4.88 5.28 L 15 15.85 L2 1.27 1.4 L3 1.4 1.75 M 2.4 3.2 R V2 26/31 Typ. 0.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 5.4 Package information TO-252 (DPAK) mechanical data Figure 45. TO-252 (DPAK) package dimension Table 9. TO-252 (DPAK) mechanical data Millimeters Dim. Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.64 0.90 B2 5.20 5.40 C 0.45 0.6 C2 0.48 0.6 D 6 6.20 D1 E 5.1 6.4 6.6 E1 4.7 e 2.28 G 4.4 4.6 H 9.35 10.1 L2 0.
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Package information VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Table 9. TO-252 (DPAK) mechanical data (continued) Millimeters Dim. Min. L4 0.6 R Max. 1 0.2 V2 0° Package weight 5.5 Typ. 8° Gr. 0.29 SO-8 mechanical data Figure 46. SO-8 package dimension Table 10. SO-8 mechanical data Millimeters Dim. Min. 28/31 Typ. Max. A 1.75 2.40 a1 0.25 0.1 a2 1.65 b 0.85 0.35 b1 0.25 0.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Table 10. Package information SO-8 mechanical data (continued) Millimeters Dim. Min. C Typ. 0.5 c1 Max. 0.25 45 D 5 4.8 E 6.2 5.8 e 1.27 e3 3.81 F 4 3.8 L 1.27 0.4 M 0.
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Revision history 6 VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Revision history Table 11. 30/31 Document revision history Date Revision Changes 21-Jun-2004 6 Initial release. 03-Apr-2009 7 Document reformatted. Added Table 1: Device summary on page 1. Updated Section 5: Package information on page 24 06-Apr-2010 8 Added part number VNS14NV04.
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VNB14NV04, VND14NV04, VND14NV04-1, VNS14NV04 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.