Datasheet

Block diagram and pin description VN5050J-E
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Figure 2. Configuration diagram (top view)
Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The
new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are
connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,
these pins should be left unconnected.
PowerSSO-12
TA B = V
cc
N.C.
OUTPUT
OUTPUT
OUTPUT
N.C.
OUTPUT
12
11
10
9
8
7
1
2
3
4
5
6
N.C.
N.C.
INPUT
STATUS_DIS
GND
STATUS
Table 3. Suggested connections for unused and N.C. pins
Connection / Pin STATUS N.C. OUTPUT INPUT STAT_DIS
Floating X X X X X
To ground N.R.
(1)
(1) Not recommended.
XN.R.
Through 10K
resistor
Through 10K
resistor