Datasheet

Electrical specifications VN5050J-E
12/31
Figure 4. Status timings
Truth Table
Table 12. Truth table
Conditions INPUT OUTPUT STATUS (V
SD
=0V)
(1)
(1) If the V
SD
is high, the STATUS pin is in a high impedance.
Normal operation
L
H
L
H
H
H
Current limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output voltage > V
OL
L
H
H
H
Lv
H
Output current < I
OL
L
H
L
H
H
(2)
L
(2) The STATUS pin becomes high with a delay equal to t
POL
after INPUT falling edge.
V
IN
V
STAT
t
POL
OPEN LOAD STATUS TIMING (without external pull-up)
I
OUT
< I
OL
V
OUT
< V
OL
t
DOL(on)
V
IN
V
STAT
OPEN LOAD STATUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
V
IN
V
STAT
OVER TEMP STATUS TIMING
t
SDL
t
SDL
T
j
> T
TSD
V
IN
V
STAT
t
DSTKON
OUTPUT STUCK TO V
CC
I
OUT
> I
OL
V
OUT
> V
OL
t
DOL(on)