Datasheet

Table Of Contents
VIPER37 Operation description
Doc ID 022218 Rev 1 27/35
After the startup time, t
SS
, during which the feedback voltage is fixed at V
FBlin
, the output
capacitor may not be at its nominal value and the controller interprets this situation as an
overload condition. In this case, the OLP delay helps to avoid an incorrect device shutdown
during the startup phase.
Owing to the above considerations, the OLP delay time must be long enough to bypass the
initial output voltage transient and check the overload condition only when the output voltage
is in steady-state. The output transient time depends on the value of the output capacitor
and on the load.
When the value of the C
FB
capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used, shown in
Figure 31
.
Using this alternative compensation network, two poles (f
PFB
, f
PFB1
) and one zero (f
ZFB
) are
introduced by the capacitors C
FB
and C
FB1
and the resistor R
FB1
.
The capacitor C
FB
introduces a pole (f
PFB
) at a higher frequency than f
ZB
and f
PFB1
. This
pole is usually used to compensate the high frequency zero due to the ESR (equivalent
series resistor) of the output capacitance of the flyback converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Figure 31
, are reported by the equations below:
Equation 6
Equation 7
Equation 8
R
FB(DYN)
is the dynamic resistance seen by the FB pin.
The C
FB1
capacitor fixes the OLP delay and usually C
FB1
results much higher than C
FB
.
Equation 5
can still be used to calculate the OLP delay time but C
FB1
must be considered
instead of C
FB
. Using the alternative compensation network, the user can satisfy, in all
cases, the loop stability and the correct OLP delay time alike.
1FB1FB
ZFB
RC2
1
f
π
=
()
1FB)DYN(FBFB
1FB)DYN(FB
PFB
RRC2
RR
f
π
+
=
()
)DYN(FB1FB1FB
1PFB
RRC2
1
f
+π
=