Datasheet

Operation descriptions VIPER27
22/31 Doc ID 15133 Rev 5
Equation 7
Equation 8
The R
FB(DYN)
is the dynamic resistance seen by the FB pin.
The C
FB1
capacitor fixes the OLP delay and usually C
FB1
results much higher than C
FB
.
The
Equation 5 can be still used to calculate the OLP delay time but C
FB1
has to be
considered instead of C
FB
. Using the alternative compensation network, the designer can
satisfy, in all case, the loop stability and the enough OLP delay time alike.
Figure 28. FB pin configuration
Figure 29. FB pin configuration
()
1FB)DYN(FBFB
1FB)DYN(FB
PFB
RRC2
RR
f
⋅⋅⋅π⋅
+
=
()
)DYN(FB1FB1FB
1PFB
RRC2
1
f
+⋅⋅π⋅
=
From sense FET
4.8V
BURST
PWM
CONTROL
Cfb
To PWM Logic
BURST-MODE
REFERENCES
BURST-MODE
LOGIC
+
-
PWM
+
-
OLP comparator
To disable logic
4.8V
From sense FET
PWM
CONTROL
+
-
PWM
BURST
To disable logic
+
-
OLP comparator
To PWM Logic
BURST-MODE
LOGIC
Cfb1
Rfb1
Cfb
BURST-MODE
REFERENCES