Datasheet

VIPER27 Operation descriptions
Doc ID 15133 Rev 5 21/31
When the feedback pin voltage reaches the threshold V
FBlin
an internal current generator
starts to charge the feedback capacitor (C
FB
) and when the feedback voltage reaches the
V
FBolp
threshold, the converter is turned off and the start up phase is activated with reduced
value of I
DDch
to 0.6 mA, see Table 7 on page 6 .
During the first start up phase of the converter, after the soft-start up time, t
SS
, the output
voltage could force the feedback pin voltage to rise up to the
V
FBolp
threshold that switches
off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The
Figure 28
on page 22
and Figure 29 show the two different feedback networks.
The time from the over load detection (V
FB
= V
FBlin
) to the device shutdown
(V
FB
= V
FBolp
) can be set by C
FB
value (see Figure 28 on page 22 and Figure 29 ), using the
formula:
Equation 5
In the
Figure 28 , the capacitor connected to FB pin (C
FB
) is part of the compensation circuit
as well as it needs to activate the over load protection (see equation 5).
After the start up time, t
SS
, during which the feedback voltage is fixed at V
FBlin
, the output
capacitor could not be at its nominal value and the controller interprets this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start up phase.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the C
FB
capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in
Figure 29 on page 22 .
Using this alternative compensation network, two poles (f
PFB
, f
PFB1
) and one zero (f
ZFB
) are
introduced by the capacitors C
FB
and C
FB1
and the resistor R
FB1
.
The capacitor C
FB
introduces a pole (f
PFB
) at higher frequency than f
ZB
and f
PFB1
. This pole
is usually used to compensate the high frequency zero due to the ESR (equivalent series
resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in
Figure 29 are reported by the equations below:
Equation 6
T
OLP delay–
C
FB
V
FBolp
V
FBlin
–
3μA
----------------------------------------
×=
1FB1FB
ZFB
RC2
1
f
⋅⋅π⋅
=