Datasheet

DocID14419 Rev 9 23/32
VIPER17 Operation descriptions
32
Figure 28. FB pin configuration
Figure 29. FB pin configuration
7.11 Burst-mode operation at no load or very light load
When the load decrease the feedback loop reacts lowering the feedback pin voltage. If it
falls down the burst mode threshold, V
FBbm
, the power MOSFET is not more allowed to be
switched on. After the MOSFET stops, as a result of the feedback reaction to the energy
delivery stop, the feedback pin voltage increases and exceeding the level, V
FBbm
+
V
FBbmhys
, the power MOSFET starts switching again. The burst mode thresholds are
reported on Table 8 and Figure 30 shows this behavior. Systems alternates period of time
where power MOSFET is switching to period of time where power MOSFET is not switching;
this device working mode is the burst mode. The power delivered to output during switching
periods exceeds the load power demands; the excess of power is balanced from not
switching period where no power is processed. The advantage of burst mode operation is
an average switching frequency much lower then the normal operation working frequency,
up to some hundred of hertz, minimizing all frequency related losses. During the burst-mode
the drain current peak is clamped to the level, I
D_BM
, reported on Table 8.
From sense FET
V
FBolp
BURST
PWM
CONTROL
Cfb
To PWM Logic
BURST-MODE
References
BURST-MODE
LOGIC
+
-
PWM
+
-
OLP comparator
To disable logic
V
FBolp
From R
SENSE
PWM
CONTROL
+
-
PWM
BURST
To disable logic
+
-
OLP comparator
To GATE driver
BURST-MODE
LOGIC
Cfb1
Rfb1
Cfb
BURST-MODE
References