Datasheet

Operation descriptions VIPER17
22/32 DocID14419 Rev 9
After the start up time, t
SS
, during which the feedback voltage is fixed at V
FBlin
, the output
capacitor could not be at its nominal value and the controller interpreter this situation as an
over load condition. In this case, the OLP delay helps to avoid an incorrect device shut down
during the start up.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the C
FB
capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29 on page 23.
Using this alternative compensation network, two poles (f
PFB
, f
PFB1
) and one zero (f
ZFB
) are
introduced by the capacitors C
FB
and C
FB1
and the resistor R
FB1
.
The capacitor C
FB
introduces a pole (f
PFB
) at higher frequency than f
ZB
and f
PFB1
. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29 are reported by the equations below:
Equation 6
Equation 7
Equation 8
The R
FB(DYN)
is the dynamic resistance seen by the FB pin.
The C
FB1
capacitor fixes the OLP delay and usually C
FB1
results much higher than C
FB
.
The Equation 5 can be still used to calculate the OLP delay time but C
FB1
has to be
considered instead of C
FB
. Using the alternative compensation network, the designer can
satisfy, in all case, the loop stability and the enough OLP delay time alike.
1FB1FB
ZFB
RC2
1
f
⋅⋅π⋅
=
()
1FB)DYN(FBFB
1FB)DYN(FB
PFB
RRC2
RR
f
⋅⋅⋅π⋅
+
=
()
)DYN(FB1FB1FB
1PFB
RRC2
1
f
+⋅⋅π⋅
=