Datasheet

Operation descriptions VIPER17
18/32 DocID14419 Rev 9
7.6 Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz
(115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of side-
band harmonics having the same energy on the whole but smaller amplitudes.
7.7 Current mode conversion with adjustable current limit set
point
The device is a current mode converter: the drain current is sensed and converted in
voltage that is applied to the non inverting pin of the PWM comparator. This voltage is
compared with the one on the feed-back pin through a voltage divider on cycle by cycle
basis.
The VIPER17 has a default current limit value, I
DLIM
, that the designer can adjust according
the electrical specification, by the R
LIM
resistor connected to the CONT see Figure 16 on
page 11.
The CONT pin has a minimum current sunk needed to activate the I
DLIM
adjustment: without
R
LIM
or with high R
LIM
(i.e. 100 KΩ) the current limit is fixed to the default value (see I
DLIM
,
Table 8 on page 7).
7.8 Overvoltage protection (OVP)
The VIPER17 has integrated the logic for the monitor of the output voltage using as input
signal the voltage V
CONT
during the OFF time of the power MOSFET. This is the time when
the voltage from the auxiliary winding tracks the output voltage, through the turn ratio
The CONT pin has to be connected to the auxiliary winding through the diode D
OVP
and the
resistors R
OVP
and R
LIM
as shows the Figure 27 on page 20 When, during the OFF time,
the voltage V
CONT
exceeds, four consecutive times, the reference voltage V
OVP
(see
Table 8 on page 7) the overvoltage protection will stop the power MOSFET and the
converter enters the auto-restart mode.
In order to bypass the noise immediately after the turn off of the power MOSFET, the voltage
V
CONT
is sampled inside a short window after the time T
STROBE
, see Table 8 on page 7 and
the Figure 26 on page 20. The sampled signal, if higher than V
OVP
, trigger the internal OVP
digital signal and increments the internal counter. The same counter is reset every time the
signal OVP is not triggered in one oscillator cycle.
Referring to the Figure 21, the resistors divider ratio k
OVP
will be given by:
N
AUX
N
SEC
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