Datasheet
Table Of Contents
- Table 1. General Features
- Figure 1. Block Diagram
- Figure 2. Package
- Table 2. Absolute Maximum Rating
- Table 3. Thermal data
- Figure 3. Connection Diagrams (Top View)
- Table 4. Current and Voltage Convention
- Table 5. Ordering Numbers
- Table 6. Avalance Characteristics
- Table 7. Power Section
- Table 8. Supply Section
- Table 9. Oscillator Section
- Table 10. Error Amplifier Section
- Table 11. PWM Comparator Section
- Table 12. Shutdown and Overtemperature Section
- Figure 4. VDD Regulation Point
- Figure 5. Undervoltage Lockout
- Figure 6. Transition Time
- Figure 7. Shutdown Action
- Figure 8. Breakdown Voltage vs. Temperature
- Figure 9. Typical Frequency Variation
- Figure 10. Start-Up Waveforms
- Figure 11. Over-temperature Protection
- Figure 12. Oscillator
- Figure 13. Error Amplifier frequency Response
- Figure 14. Error Amplifier Phase Response
- Figure 15. Avalanche Test Circuit
- Figure 16. Offline Power Supply With Auxiliary Supply Feedback
- Figure 17. Offline Power Supply With Optocoupler Feedback
- Figure 18. Behaviour of the high voltage current source at start-up
- Figure 19. Mixed Soft Start and Compensation
- Figure 20. Latched Shut Down
- Figure 21. Typical Compensation Network
- Figure 22. Slope Compensation
- Figure 23. External Clock Sinchronisation
- Figure 24. Current Limitation Circuit Example
- Figure 25. Input Voltage Surges Protection
- Figure 26. Recommended Layout
- Figure 27. Pentawatt HV Tube Shipment ( no suffix )
- Table 13. Revision history

VIPer100/SP - VIPer100A/ASP
5/24
Table 8. Supply Section
Table 9. Oscillator Section
Table 10. Error Amplifier Section
Symbol Parameter Test Conditions‘ Min Typ Max Unit
I
DDch
Start-Up Charging Current
V
DD
= 5V; VDS = 35V
(see Figure 5)(see Figure 18)
-2 mA
I
DD0
Operating Supply Current
V
DD
= 12V; F
SW
= 0kHz
(see Figure 5)
12 16 mA
I
DD1
Operating Supply Current
V
DD
= 12V; F
sw
= 100kHz
15.5 mA
V
DD
= 12V; F
sw
= 200kHz
19 mA
V
DDoff
Undervoltage Shutdown (see Figure 5) 7.5 8 9 V
V
DDon
Undervoltage Reset (see Figure 5) 11 12 V
V
DDhyst
Hysteresis Start-up (see Figure 5) 2.4 3 V
Symbol Parameter Test Conditions‘ Min Typ Max Unit
F
SW
Oscillator Frequency Total
Variation
R
T
=8.2KΩ; C
T
=2.4nF
V
DD
=9 to 15V;
with R
T
± 1%; C
T
± 5%
(see Figure 9)(see Figure 12)
90 100 110 KHz
V
OSCIH
Oscillator Peak Voltage 7.1 V
V
OSCIL
Oscillator Valley Voltage 3.7 V
Symbol Parameter Test Conditions‘ Min Typ Max Unit
V
DDREG
V
DD
Regulation Point I
COMP
=0mA (see Figure 4)
12.6 13 13.4 V
ΔV
DDreg
Total Variation
T
j
=0 to 100°C
2%
G
BW
Unity Gain Bandwidth
From Input =V
DD
to
Output = V
COMP
COMP pin is open
(see Figure 13)
150 KHz
A
VOL
Open Loop Voltage Gain
COMP pin is open
(see Figure 13)
45 52 dB
G
m
DC Transconductance
V
COMP
=2.5V(see Figure 4)
1.1 1.5 1.9 mA/V
V
COMPLO
Output Low Level
I
COMP
=-400µA; V
DD
=14V
0.2 V
V
COMPHI
Output High Level
I
COMP
=400µA; V
DD
=12V
4.5 V
I
COMPLO
Output Low Current Capability
V
COMP
=2.5V; V
DD
=14V
-600 µA
I
COMPHI
Output High Current
Capability
V
COMP
=2.5V; V
DD
=12V
600 µA