Datasheet
Table Of Contents
- Table 1. General Features
- Figure 1. Block Diagram
- Figure 2. Package
- Table 2. Absolute Maximum Rating
- Table 3. Thermal data
- Figure 3. Connection Diagrams (Top View)
- Table 4. Current and Voltage Convention
- Table 5. Ordering Numbers
- Table 6. Avalance Characteristics
- Table 7. Power Section
- Table 8. Supply Section
- Table 9. Oscillator Section
- Table 10. Error Amplifier Section
- Table 11. PWM Comparator Section
- Table 12. Shutdown and Overtemperature Section
- Figure 4. VDD Regulation Point
- Figure 5. Undervoltage Lockout
- Figure 6. Transition Time
- Figure 7. Shutdown Action
- Figure 8. Breakdown Voltage vs. Temperature
- Figure 9. Typical Frequency Variation
- Figure 10. Start-Up Waveforms
- Figure 11. Over-temperature Protection
- Figure 12. Oscillator
- Figure 13. Error Amplifier frequency Response
- Figure 14. Error Amplifier Phase Response
- Figure 15. Avalanche Test Circuit
- Figure 16. Offline Power Supply With Auxiliary Supply Feedback
- Figure 17. Offline Power Supply With Optocoupler Feedback
- Figure 18. Behaviour of the high voltage current source at start-up
- Figure 19. Mixed Soft Start and Compensation
- Figure 20. Latched Shut Down
- Figure 21. Typical Compensation Network
- Figure 22. Slope Compensation
- Figure 23. External Clock Sinchronisation
- Figure 24. Current Limitation Circuit Example
- Figure 25. Input Voltage Surges Protection
- Figure 26. Recommended Layout
- Figure 27. Pentawatt HV Tube Shipment ( no suffix )
- Table 13. Revision history
VIPer100/SP - VIPer100A/ASP
19/24
Figure 26. Recommended Layout
Layout Considerations
Some simple rules insure a correct running of switching power supplies. They may be classified into two
categories:
- Minimizing power loops: The switched power current must be carefully analysed and the corresponding
paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances,
especially on secondary side.
- Using different tracks for low level and power signals: Interference due to mixing of signal and power
may result in instabilities and/or anomalous behaviour of the device in case of violent power surge (Input
overvoltages, output short circuits...).
In case of VIPer, these rules apply as shown on (see Figure 26).
• Loops C1-T1-U1, C5-D2-T1, and C7-D1-T1 must be minimized.
• C6 must be as close as possible to T1.
• Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power
source of the device.
T1
U1
VIPerXX0
13V
OSC
COMP SOURCE
DRAINVDD
-
+
C4
C2
C5
C1
D2
R1
R2
D1
C7
C6
C3
ISO1
Fr om input
d
iodes bridge
To secondar y
filtering and loa
d
FC00500