Datasheet
Table Of Contents
- Table 1. General Features
- Figure 1. Block Diagram
- Figure 2. Package
- Table 2. Absolute Maximum Rating
- Table 3. Thermal data
- Figure 3. Connection Diagrams (Top View)
- Table 4. Current and Voltage Convention
- Table 5. Ordering Numbers
- Table 6. Avalance Characteristics
- Table 7. Power Section
- Table 8. Supply Section
- Table 9. Oscillator Section
- Table 10. Error Amplifier Section
- Table 11. PWM Comparator Section
- Table 12. Shutdown and Overtemperature Section
- Figure 4. VDD Regulation Point
- Figure 5. Undervoltage Lockout
- Figure 6. Transition Time
- Figure 7. Shutdown Action
- Figure 8. Breakdown Voltage vs. Temperature
- Figure 9. Typical Frequency Variation
- Figure 10. Start-Up Waveforms
- Figure 11. Over-temperature Protection
- Figure 12. Oscillator
- Figure 13. Error Amplifier frequency Response
- Figure 14. Error Amplifier Phase Response
- Figure 15. Avalanche Test Circuit
- Figure 16. Offline Power Supply With Auxiliary Supply Feedback
- Figure 17. Offline Power Supply With Optocoupler Feedback
- Figure 18. Behaviour of the high voltage current source at start-up
- Figure 19. Mixed Soft Start and Compensation
- Figure 20. Latched Shut Down
- Figure 21. Typical Compensation Network
- Figure 22. Slope Compensation
- Figure 23. External Clock Sinchronisation
- Figure 24. Current Limitation Circuit Example
- Figure 25. Input Voltage Surges Protection
- Figure 26. Recommended Layout
- Figure 27. Pentawatt HV Tube Shipment ( no suffix )
- Table 13. Revision history
VIPer100/SP - VIPer100A/ASP
17/24
Over-Temperature Protection
Over-temperature protection is based on chip temperature sensing. The minimum junction temperature at
which over-temperature cut-out occurs is 140ºC, while the typical value is 170ºC. The device is
automatically restarted when the junction temperature decreases to the restart temperature threshold that
is typically 40ºC below the shutdown value (see Figure 11) page 8..
Figure 19. Mixed Soft Start and Compensation Figure 20. Latched Shut Down
Figure 21. Typical Compensation Network Figure 22. Slope Compensation
Figure 23. External Clock Sinchronisation Figure 24. Current Limitation Circuit Example
AUXILIAR
Y
WINDING
-
+
13V
OSC
COMP SOURCE
DRAINVDD
U1
VIPER100
R1
C1
+
C2
D1
R2
R3
D2
D3
+
C3
FC00131
C4
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
Shutdown
U1
Q1
Q2
R1
R2R3
R4
D1
FC00110
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
U1
R1
C1
FC00121
C2
FC00141
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
R1R2
Q1
C2
C1 R3
U1
C3
-
+
13V
OSC
COMP SOURCE
DRAINVDD
U1
VIPER100
10 kΩ
FC00220
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
U1
R1
R2
Q1
FC00240