Datasheet

VIPer100/SP - VIPer100A/ASP
14/24
High Voltage Start-up Current Suorce
An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up
phase. This current is partially absorbed by internal control circuits which are placed into a standby mode
with reduced consumption and also provided to the external capacitor connected to the V
DD
pin. As soon
as the voltage on this pin reaches the high voltage threshold V
DDon
of the UVLO logic, the device
becomes active mode and starts switching. The start-up current generator is switched off, and the
converter should normally provide the needed current on the V
DD
pin through the auxiliary winding of the
transformer, as shown on (see Figure 18).
In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage
supply current to the V
DD
pin (i.e. short circuit on the output of the converter), the external capacitor
discharges to the low threshold voltage V
DDoff
of the UVLO logic, and the device goes back to the inactive
state where the internal circuits are in standby mode and the start-up current source is activated. The
converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging
current towards discharging when the VIPer100/100A tries to start. This ratio is fixed by design to 2A to
15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W,
for a 230Vrms input voltage.
This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the
transformer when a short circuit occurs.
The external capacitor C
VDD
on the V
DD
pin must be sized according to the time needed by the converter
to start up, when the device starts switching. This time t
SS
depends on many parameters, among which
transformer design, output capacitors, soft start feature, and compensation network implemented on the
COMP pin. The following formula can be used for defining the minimum capacitor needed:
where:
I
DD
is the consumption current on the V
DD
pin when switching. Refer to specified I
DD1
and I
DD
2 values.
t
SS
is the start up time of the converter when the device begins to switch. Worst case is generally at full
load.
V
DDhyst
is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).
The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also
used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of
the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics
of (see Figure 19) can be used. It mixes a high performance compensation network together with a
separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be
adjusted separately.
If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing
start-up cycles, and the V
DD
voltage is oscillating between V
DDon
and V
DDoff
.
This voltage can be used for supplying external functions, provided that their consumption does not
exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched
shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the
input voltage is removed.
C
VDD
I
DD
t
SS
V
DDhyst
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