Datasheet

USBLC6-4 Technical information
Doc ID 11068 Rev 4 9/13
2.6 PSPICE model
Figure 16. shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes
are defined by the PSPICE parameters given in Figure 17.
Figure 16. PSPICE model
Note: This simulation model is available only for an ambient temperature of 27 °C.
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow
MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
VBUS
LIO
io1
RIO
LIO
io2
GND
RIO
LIO
RIO
io3
MODEL = Dzener LIO
RIO
LIO
io4
RIO
RGNDLGND
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
MODEL = Dlow
MODEL = Dhigh
MODEL = Dlow MODEL = Dhigh
VBUS
LIO
io1
RIO
LIO
io2
GND
RIO
LIO
RIO
io3
MODEL = Dzener LIO
RIO
LIO
io4
RIO
RGNDLGND
Figure 17. PSPICE parameters Figure 18. USBLC6-4SC6 PCB layout
considerations
0.1u0.1u0.1uTT
0.60.60.6VJ
0.420.630.38RS
0.33330.33330.3333M
1.241.131.62N
100p100p100pISR
3.21p2.27f55.2pIS
2.420.0180.038IKF
1m1m1mIBV
20p2.4p2.4pCJ0
7.35050BV
DzenerDhighDlow
0.1u0.1u0.1uTT
0.60.60.6VJ
0.420.630.38RS
0.33330.33330.3333M
1.241.131.62N
100p100p100pISR
3.21p2.27f55.2pIS
2.420.0180.038IKF
1m1m1mIBV
20p2.4p2.4pCJ0
7.35050BV
DzenerDhighDlow
50mRGND
430pLGND
100mRIO
710pLIO
50mRGND
430pLGND
100mRIO
710pLIO
D+1
C = 100nF
BUS
D-1
GND
USBLC6-4SC6
D+2
D-2
V
BUS
1