Datasheet

USBLC6-4 Technical information
Doc ID 11068 Rev 4 5/13
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the USBLC6-4SC6 provides high immunity to ESD surge, efficient protection depends
on the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to the V
BUS
pin and from GND plane to GND pin must be as short
as possible to avoid overvoltages due to parasitic phenomena (see Figure 7 and Figure 8 for
layout considerations)
V
BUS
L
I/O
L
VBUS
L
GND
L
I/O
L
GND
V pin
CC
V
CL
V
F
I/O pin
V
TRANSIL
V+V
TRANSIL F
-V
F
V
CL-
t = 1 ns
r
t
t
t = 1 ns
r
V
CL+
GND pin
Data line
Positive
Surge
Negative
Surge
ESD sur ge on data line
di
dt
L
I/O
+ L
GND
di
dt
di
dt
-L
I/O
- L
GND
di
dt
di
dt
V
+
=V +V + L + L
sur ge > 0
CL TRANSIL F I/O GND
V = -V - L - L
sur ge > 0
CL- F I/O GND
di
dt
di
dt
di
dt
di
dt
di
dt
Rd.IpVV
BR
TRANSIL
+=
Figure 7. ESD behavior: optimized layout and
addition of a capacitance of 100 nF
Figure 8. ESD behavior: measurement
conditions (with coupling
capacitance)
Unsuitable layout
Optimized layout
TEST BOARD
V
bus
ESD SURGE
OUT
IN
USBLC6-4SC6