Datasheet

USBLC6-2 Technical information
Doc ID 11265 Rev 5 5/14
We can significantly reduce this phenomena with simple layout optimization. It is for this
reason that some recommendations have to be followed (see 2.3: How to ensure good ESD
protection).
Figure 6. ESD behavior: parasitic phenomena due to unsuitable layout
2.3 How to ensure good ESD protection
While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on
the layout of the board. In the same way, with the rail to rail topology, the track from data
lines to I/O pins, from V
CC
to V
BUS
pin and from GND plane to GND pin must be as short as
possible to avoid overvoltages due to parasitic phenomena (see Figure 6. and Figure 7. for
layout consideration)
V
BUS
L
I/O
L
VBUS
L
GND
L
I/O
L
GND
V pin
CC
V
CL
V
F
I/O pin
V
TRANSIL
V+V
TRANSIL F
-V
F
V
CL-
t = 1 ns
r
t
t
t = 1 ns
r
V
CL+
GND pin
Data line
Positive
Surge
Negative
Surge
ESD surge on data line
di
dt
L
I/O
+ L
GND
di
dt
di
dt
-L
I/O
- L
GND
di
dt
di
dt
V
+
=V +V + L + L
surge > 0
CL TRANSIL F I/O GND
V = -V - L - L
surge > 0
CL- F I/O GND
di
dt
di
dt
di
dt
di
dt
di
dt
Rd.IpVV
BR
TRANSIL
+=
Figure 7. ESD behavior: layout optimization Figure 8. ESD behavior: measurement
conditions
Unsuitable layout
Optimized layout
1 1
6
2
5
3
4
1 1
6
2
5
3
4
+5 V
IN OUT
TEST BOARD
ESD SURGE
USBLC6-2SC6